Circuit Board Layout Guidelines for White LED Charge Pumps
Observe the following guidelines when laying out PCB artwork for the MAX1576 white-LED charge pump:
- Connect all GND and PGND pins to the exposed paddle (EP) directly under the IC.
- Use only ceramic capacitors with X5R dielectric or better for the input, output, and flying capacitors. Low ESR in very important for high-output current drive, low input/output ripple, and stable operation.
- To prevent switching noise from upsetting the IC's bias circuits, place the input capacitors (CIN and CINP) as close to the input and ground pins as possible, preferably with no vias between the capacitor and IC.
- If there are separate GND and PGND and/or IN and PIN pins, then the IC includes separate inputs for power and bias. If these pins are not close together, then two input capacitors should be used: CINP from PIN to PGND, and CIN from IN to GND, each as close to the IC as possible. In this case, PIN and PGND should connect to the system power and ground planes, while IN and GND are kept locally quiet to the IC. Route PCB power first to CINP and INP, and then through some vias to CIN and IN to provide some input noise filtering at IN. PGND and GND should only connect to each other through the exposed paddle.
- To ensure charge-pump regulation stability, place the output capacitor, COUT, as close to the OUT pin as possible. Connect COUT's ground terminal to the nearest PGND or GND pin or to the exposed paddle (EP).
- To ensure low output impedance from the charge pump, place the flying capacitors, C1 and C2, as close to the IC as possible. If vias cannot be avoided, it is better to have them in series with C1 and/or C2 than in series with CIN or CINP because the flying capacitors have no effect on regulator stability.
- Connect the ground terminals of any reference bypass capacitors (there are none on the MAX1576) or setting resistors (RM and RF on MAX1576) to the GND pin (as opposed to PGND). This reduces noise coupling into the analog blocks of the IC.
- An optional large via in the exposed paddle (EP) may be useful for inspecting the solder joint and also to facilitate removal of the IC from the PCB with a soldering iron.
- Route the logic input traces and connections to the LEDs as long as needed. Vias on these lines cause no problem because current is regulated on these outputs. Ripple on these lines, however, may affect RF circuits if routed too close to sensitive radio circuits.