DS33Z11 - Ethernet LAN To Unframed T1/E1 WAN Bridge
DesignWhen designing equipment for telecommunication use, it is important that the integrity of the interconnected data signals be maintained for error-free operation. The board should have a separate power and ground plane, and the power supply should be decoupled to reduce noise.
The main component of the LAN-to-WAN bridge is the Maxim ELITE product line, specifically the DS33Z11, a single-port 10/100 Ethernet-to-serial interface. The device bridges an Ethernet connection and a serial connection (also know as a WAN connection), such as T1, E1, T3, E3, or HDSL. The device is composed of a 10/100 Ethernet MAC, packet arbiter, committed information rate controller, HDLC/X.86 mapper, SDRAM interface, bit-error-rate tester (BERT), and control logic.
The ELITE line of devices performs two tasks. First, the DS33Z11 encapsulates the LAN Ethernet traffic with HDLC or X.86 (LAPS) for transmission over the WAN interface. Secondly, the DS33Z11 extracts encapsulated Ethernet packets received from the WAN interface for transmission over the LAN interface. The DS33Z11 can be configured by interfacing to a microcontroller which allows interactive control, by using a serial EEPROM which allows easy one-time power-up configuration, or by directly biasing the hardware pins, which allows operation with no external components.
The physical connection to the WAN is provided by the Maxim DS21348 T1/E1/J1 single-port line interface. The DS21348 performs all the functions necessary for interfacing at the physical layer to a T1, E1, or J1 line. The receiver performs clock and data recovery, signal decoding, and loss-of-signal monitoring. The transmitter performs signal encoding and drives standard-compliant waveforms onto 100Ω or 120Ω unshielded, twisted-pair cable or 75Ω coaxial cable. A built-in jitter attenuator can be mapped into the receive or transmit path.
The physical connection to the LAN is provided by the National Semiconductor® DP83846A single-port 10/100 Ethernet transceiver. This transceiver, also know as a physical layer device (PHY), supports both 10Base-T and 100Base-TX Ethernet protocols over Category 3 or Category 5 unshielded twisted-pair cable. Digital-signal-processor technology and digital phase-lock loops are used in the transmit and receive circuitry. This results in enhanced performance, better noise immunity, and fewer external components.
The remaining components are comprised of the microcontroller and associated circuitry, 128Mb synchronous dynamic RAM (SDRAM), crystal oscillators, transformers, RJ-45 connectors, resistors, capacitors, and an external or on-board 3.3V power supply. Figure 1 and Table 1 show all the components necessary to build the LAN-to-WAN bridge, excluding the power supply.
The circuit is straightforward with the DS33Z11 connected to the DS21348 on the WAN side and to the DP83846A on the LAN side. The DS21348 interfaces directly to the DS33Z11 through the transmit and receive serial and clock connections. The DP83846A interfaces directly to the DS33Z11 through the IEEE® 802.3 media independent interface (MII) connections. The configuration of the DS33Z11, DS21348, and DP83846A is performed by the microcontroller. However, if cost is a factor and reconfiguration of the devices not an issue, all the devices support configuration without using a microcontroller. While the DS33Z11 may need an external EEPROM to support certain hardware-only configurations, the DS21348 and DP83846A are configured through preset voltages present on external pins. The 25MHz oscillator is needed for the Ethernet interface and the 1.544MHz or 2.048MHz oscillator is needed for the T1 or E1 interface. If the DS21348 recovered clock also drives the transmit clock, it is possible to use the internal PLL to operate in T1 or E1 mode with only a 2.048MHz oscillator. Because every application is slightly different, the remaining circuit connections are left to the designer. For further assistance with the device, please use the links found in the References section below.
Figure 1. Block diagram of the ethernet LAN to unframed, T1/E1 WAN bridge.
Table 1. Part Listing of the Ethernet LAN to Unframed, T1/E1 WAN Bridge
|DS33Z11||1||3.3V/1.8V single-port Ethernet-to-serial interface||Maxim Integrated|
|DS21348||1||3.3V single-port T1/E1 line interface unit (LIU)||Maxim Integrated|
|DP83846A||1||3.3V single-port 10/100 Ethernet transceiver||National Semiconductor|
|MT48LCM32B2||1||3.3V 128Mb SDRAM||Micron Technology|
|Microcontroller||1||3.3V 8- or 16-bit microcontroller||Various|
|NTH089AA3-25.0000||1||25.000MHz oscillator, 3.3V||Saronix|
|NTH089AA3-1.5440||1||1.544MHz oscillator, 3.3V||Saronix|
|NTH089AA3-2.0480||1||2.048MHz oscillator, 3.3V||Saronix|
|H1012B or PE-68515L||1||16-pin SMT 1:1CT 10/100Base-T transformer||Pulse Engineering|
|TX1099||1||16-pin SMT multitap transformer||Pulse Engineering|
|RJ-45 Jack||2||8-Pin, RJ-45 right-angle jack||Various|
|Power supply/connector||1||Power-supply circuitry||Various|
|Resistor||Pullup and bias resistors||Various|
|Capacitor||Power and decoupling capacitors||Various|
|LED||Power, LAN, and WAN connection indication||Various|
For further questions on the LAN-to-WAN bridge design, please contact the Telecommunication Applications support team by email, , or telephone at 972-371-6555.