Single-coil latching relays are found in applications including signal routing, audio, and automotive systems. These relays can pose a design challenge because coil current must flow in both directions through a single coil (Figure 1
). Current flowing from pin 8 to pin 1 causes the relay to latch in its reset position, and current flowing from pin 1 to pin 8 latches the relay in its set position. The relay maintains its position even when the coil current is removed. Power is saved by removing coil current after the relay latches.
Figure 1. Current flow in a single coil latches the corresponding relay in its SET or RESET position.
A simple circuit that drives up to four single-coil latching relays (Figure 2
) includes a parallelinterface relay driver (U1) with open-drain outputs (Figure 3
) and inductive-kickback protection. Latch any of the four relays to their set or reset positions by turning on the corresponding output (OUTX). That output is selected by asserting its digital address on pins A2 to A0 while active-low CS is high. Activate the output by toggling active-low CS (Figure 4
Figure 2. This circuit easily drives four, single-coil latching relays.
Figure 3. This diagram shows two of the eight open-drain outputs from the circuit of Figure 2.
Figure 4. Interface timing for the circuit in Figure 2 illustrates the activated output.
Current flows into the enabled open-drain output and latches the relay to its set or reset position, according to the direction of the coil current. Drive active-low RESET low to turn off all enabled open-drain outputs, as soon as the relays latch to ensure lowest power consumption. Observe the set/reset timing shown in Figure 4. Do not pull active-low RESET low until the required time (tSET/RESET
)has elapsed. Waiting tSET/RESET
after the last active-low CS toggle ensures that all selected relays will properly latch to their intended positions.
Clamping diodes on each OUTX pin catch highvoltage transients that occur when the coil current is interrupted. Those diodes, as shown in Figure 2, clamp the OUTX voltage at VCC
A similar article appeared in the February, 2004 issue of EET.