Keywords: exposed pad, exposed-pad, EP, power dissipation, TDFN, TQFN, QFN, TSSOP, TDFN, TQFN, TQFP, µMAX, µSOP, QSOP, QFN, QFND, LQFP, SOIC(N), TSSOP HYBRID
An exposed pad is an exposed metal plate on an IC package. This application note describes pads that are located on the bottom of the package.
The exposed pad is plated with the same metal or metal alloy as the leads of the IC, usually tin.
The following is a partial list of package types that offer exposed pads as a standard or an optional configuration. New package types are always in development.
Exposed pads are most often employed increase the maximum power dissipation of a package. The junction-to-case resistance (θJC) listed in the data sheet of a device with an exposed pad assumes the exposed pad is soldered or thermally bonded to a PCB, unless otherwise noted.
The data sheet for a device with an exposed pad will provide instruction as to the voltage to which the exposed pad should be connected. In most applications, the exposed pad is connected to ground, but take care to verify this on every device. A blind assumption here can provide a low-impedance short that can take many hours to analyze and a PCB revision to correct.
The pad's dimensions come from the package drawing. Some exposed pad packages have variants with different-sized exposed pads. If the data sheet is not explicit as to which variant is used, contact Technical Support to obtain further information. Create the PCB footprint with information from IPC to ensure proper allowances for both IC package tolerance and process variance.
In addition to the IPC information, here are some general guidelines for creating the exposed pad's land pattern:
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APPLICATION NOTE 3273,AN3273, AN 3273, APP3273, Appnote3273, Appnote 3273
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