APPLICATION NOTE 3272

DS1624 2-Wire Communication SDA Hold Time Clarification


Abstract: The 2-Wire timing specification of the DS1624 differs from that of I²C. This application note details the difference. SDA is not held internally by the DS1624. It is the bus master's responsibility to hold SDA until after the falling edge of SCL is completed.

Introduction

This application note details the difference between DS1624 communication timing and the I²C specification. Under I²C, the SCL and SDA lines are allowed to transition simultaneously because SDA is delayed internally by the slave device for at least 300ns. The DS1624 does not delay the SDA signal with respect to SCL therefore SDA must be held in the proper logic state by the bus master until SCL has fully transitioned to logic low to prevent false generation ofSTART or STOP operations.

Proper Timing

The DS1624's SDA line does not have an internal delay relative to SCL. For this reason the SDA logic level must be held external to the DS1624 until SCL has transitioned to logic low when writing data; otherwise a start or stop condition may be recognized instead. When writing a logic "1" on the 2-wire bus, SCL must reach the guaranteed logic low threshold VIL (0.3 x VDD maximum) before SDA transitions below the guaranteed logic high threshold VIH (0.7 x VDD minimum). When writing a logic "0", SCL must reach VIL before SDA transitions above VIL. When generating a START condition, SDA must reach VIL before SCL transitions below VIH. When generating a STOP condition, SDA must reach VIH before SCL transitions below VIH. Both VIL and VIH levels are production tested on each device. This guarantees proper operation using this timing over the full voltage and temperature ranges including device fabrication tolerances.

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Figure 1.

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Figure 2.

Summary

There is a difference between the DS1624 timing and I²C specifications. The DS1624 does not internally delay SDA with respect to SCL. The system host is therefore required to maintain SDA during the falling edge of SCL to prevent logic '1's from being interpreted as START conditions and logic '0's from being interpreted as STOP conditions.