Keywords: lowpass filter, step response, time-domain response, signal conditioning, switched-capacitor filter, SC filter
The Figure 1 circuit allows lower cutoff frequencies without sacrificing the step-response time. A window comparator monitors the delta (difference) between the filter's input and output. When the delta exceeds ±50mV, the filter increases its slew rate by increasing its cutoff frequency an order of magnitude.
Figure 1. This lowpass filter maintains a fast step response by dynamically adjusting its cutoff frequency.
The switched-capacitor filter (U1) normally operates as a self-clocked device. Capacitors C1 and C2 set the cutoff frequency at 0.1Hz, and other circuitry forms a dynamic window comparator. Transistor pairs Q1-Q2 and Q3-Q4 form a complementary current mirror whose output flows through R2 and R3, creating a delta of ±50mV. Connecting the output voltage to the center tap of the two resistors centers the delta on the output voltage. You therefore set the window comparator's upper threshold at VOUT + 50mV, and the lower threshold at VOUT - 50mV.
The original input signal is lowpass-filtered by R4 and C3, producing a cutoff frequency (312Hz) that reduces sensitivity to momentary glitches. The filtered input drives the window-comparator input. If that input is outside the ±50mV window, comparator U2A or U2B will assert its output low. The low output drives Q5 into cutoff, causing its collector to assume a high impedance. Because the Q5 collector no longer grounds capacitor C2, the filter's cutoff frequency increases by ten times. When the system output changes to within 50mV of the system input, the cutoff frequency throttles back to its quiescent state.
This effect can be seen in a scope photo (Figure 2). The top trace is a step from 1.5V to 2.5V, the middle trace is the output with optimization circuitry enabled, and the bottom trace shows the filter's unmodified response. The optimized response includes a slight perturbation during the cutoff-frequency transition, but is five times faster than that of the unmodified circuit.
Figure 2. Time-domain response for the Figure 1 circuit, with optimization circuitry (middle trace) and without it (bottom trace).
The circuit shown is configured for very low cutoff frequencies, but it can be rescaled to higher frequencies by changing C1 and C2, where the oscillation frequency fOSC (in kHz) is 30 x 103/COSC (in pF), and the cutoff frequency is fOSC/100. R2 and R3 can be modified for different window values in which the delta equals the resistance multiplied by 115µA. The comparator must be an open-drain type.
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APPLICATION NOTE 3203,AN3203, AN 3203, APP3203, Appnote3203, Appnote 3203
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