Figure 1. Battery charging is controlled by the baseband µP. If the µP stalls, the chances of damaging the battery by overcharging are high.
This charging scheme can present a problem if the baseband processor locks up. Damage can occur if the charger is connected directly to the battery for any length of time. What is needed is a simple add-on circuit that monitors the PWM input and disables the series power switch if the PWM input is inactive for more than a predetermined period of time. Ideally, this circuit protection should operate independently of the processor, and be capable of restarting should the PWM signal return.
In the circuit of Figure 2, a MAX6321-HPUK30-CY power-on reset plus watchdog device (IC1) gates the PWM input with a MAX4514-CUK normally open SPST analog switch (IC2). R4, D2, and C1 protect the two ICs when the wall cube places excessive voltage on the Vcc line. Because the quiescent current of the additional circuit is very low (30µA), the choice of R4 is non-critical. R4 is chosen to provide just enough current to activate the "knee" characteristic in the zener diode (0.5mA). When the charger is unplugged, no power reaches the protection circuit, and thus it doesn't burden the battery.
Figure 2. Adding IC1and IC2 provides battery protection in the event that the processor stalls.
The RESET/ output is used to produce a CHARGER READY/ interrupt signal. When high, this signal permits the baseband controller CPU to operate, causing the PWM signal to be activated. The open-drain structure of RESET/ allows it to connect to another part of the circuit operating from the same or a different supply voltage. Thus when the charger isn't required, the watchdog and PWM circuit are powered down.
The sequence of events begins with an active charger connected to the charger input socket. When the supply voltage on Vcc reaches above 3V (for the version of the MAX6321 whose part number includes "-30"), the Reset period begins. Two hundred milliseconds later, Reset/ goes high, closing the SPST analog switch and routing the PWM input to Q1 via R1. At the same time, the watchdog input goes active and monitors the PWM input. If a transition, either positive or negative, is not received at WDI within 1.6secs, RESET/ becomes active, disabling the PWM input, and pausing the charger algorithm via the CPU interrupt (Charger Ready Signal).
Both ICs are available in 5-lead SOT23 packages, and thus the additional space required by the protection circuit is minimal.
Figures 3 and 4 show the timing relationships between incoming charger supply, Reset and Watchdog.
Figure 3. Reset timing relationship.
Figure 4. Watchdog input timing relationship.
Vcc is the charger input supply. When the charger supply is connected and rising through 3V, the MAX6321 enters the Reset period trp. Charging is disabled during this period. At Reset timeout, charging is enabled when the baseband PWM signal is connected to the series power switch.
The Watchdog input monitors the incoming baseband PWM charging control signal at the end of the Reset timeout period. If no activity is detected by the Watchdog input, the Reset timeout period is activated, and the sequence begins again. In this way, while the charger is connected, the battery is checked every 1.8s; when the baseband PWM signal becomes active, the series power switch is again enabled, allowing the PWM signal to determine the duty cycle by which the charger connects to the battery.