Keywords: ism transmitter, frac-n, fractional-n, integer-n, synthesizer, pll, channel, spacing, phase noise loop, filter, bandwidth, synthesizer IC, ism, transmitter, rf, rfic, wireless, radio frequency, rf ics, rfics
When choosing a synthesizer IC, the first decision that must be made is whether to use an integer-N or fractional-N model. A well designed sigma delta Fractional-N Synthesizer can yield superior performance in terms of phase noise, PLL lock time and comparison spur suppression. However, while the cost of fractional-N synthesizers continues to drop, integer-N synthesizer ICs still offer a less expensive solution. Understanding how performance parameters can be traded will help in making a more informed decision about what synthesizer to use.
A higher comparison frequency can significantly reduce the in-loop phase noise of the LO signal being created. Phase noise is proportional to the main synthesizer divider value (N). By increasing the comparison frequency, a lower value for N is required to achieve the same RF frequency, thus lowering the divider's noise contribution. The decrease in phase noise can then be calculated by
The benefit of increasing the loop bandwidth is a shorter lock time. Lock time is inversely proportional to the loop filter's cutoff frequency so increasing the loop bandwidth decreases the time it takes for a PLL to lock. In many applications lock time is a critical parameter and the wide loop bandwidths compatible with fractional-N synthesizers can prove invaluable.
The downside to an increased loop bandwidth is that the phase detector noise is now integrated over a larger bandwidth. Phase noise is constant through the loop filter corner frequency and begins to roll off after that. Thus, as the loop filter corner is pushed farther out, the integrated phase error of the LO signal is increased according to the following equation: Integrated Noise = 10 x log(F2/F1) where F1 and F2 are the narrow and wide loop bandwidths respectively.
The fractional-n synthesizer being used has 4 bits, which gives it a modulus 16 fractional component. This allows the comparison frequency to be eight times larger than the integer case while providing a 50 percent smaller achievable step size. If a larger modulus fractional synthesizer were used this difference could be made even greater.
As can be seen from the phase noise plots, the difference in in-band phase noise is (-73.00 - -82.83) = 9.83dB. This is very close to the theoretical difference based on the different N divider values of 10 * log (5856/732) = 9.03dB. Hence the fractional synthesizer has provided an improvement for in-band phase noise. However, when integrated phase noise is calculated the two values converge to -29dBc and -30dBc for the integer and fractional methods respectively. The wider bandwidth used in the fractional case has removed the initial phase noise advantage but created a PLL lock time improvement of approximately 5X.