High-Speed ADC Sets Input Common-Mode Range
For single supply circuits, the input signal feeding the drive amplifier and ADC should be biased at a DC level well within the VCM range. This arrangement removes a performance hurdle for the amplifier and ADC, because they don't have to maintain low distortion and linearity at 0V.
The importance of VCM for the ADC is apparent when you consider the following:
- With variation in the supply voltage (VDD), signals sourced by the RF quadrature demodulator present a wide range of common-mode voltages to the ADC.
- Input common-mode levels extending beyond the ADC's VCM range generate harmonic distortion that reduces the dynamic range. A proper VCM dc bias therefore optimizes the amplifier and ADC linearity, minimizing distortion and improving the bit-error rate (BER).
Figure 1. This high-speed ADC (U1) uses its COM output to set a precise common-mode level.
Simplifying the translation of VCM are U1's dc common mode output (COM, pin 1), REFIN (pin 46), and REFOUT (pin 45). COM provides a dc output (VDD/2) that matches the input common-mode range of U1 despite VDD variations. REFIN and REFOUT set the ADC full-scale range via resistor divider R23–R24, thereby optimizing the input amplifier SFDR and ADC dynamic range.
U2 and U3 are configured for
FS = R24/(R23+R24) x REFOUT. (REFOUT = 2.048V)
The COM voltage (pin 1 of U1) equals VDD/2, or 1.5V when VDD = 3V. This voltage also equals the input VCM range of U1. Thus, as VDD changes with temperature and supply-voltage tolerance, COM and VCM track each other to ensure a proper matching of dc voltage levels. The COM pin sources 5mA, and can be used as needed to set the dc level of other circuit elements in the system. Because the COM internal buffers are powered down during ADC shutdown, this level-setting approach saves more power than does a continuously on, 2-resistor voltage divider.
A typical application for the Figure 1 circuit is a WCDMA receiver, for which the input signal to each ADC channel is one-half the 3.84Mcps chip rate. Two benefits follow when the signal is over-sampled by U1 at four times the chip rate (Fclk = 15.36MHz). First, oversampling eases the design of an anti-alias filter by pushing the image beyond two octaves, to 13.44MHz and 17.28MHz (FI = Fs ± Fa). Second, oversampling yields a processing gain of 6dB: SNR = 10log(Fs/2BW).
U1's digital outputs are supplied by OVDD = +1.8V, which helps to minimize power consumption. The +1.8V bus lowers digital signal swings, which reduces power according to the relation P = CV2F (once for each line of the
Other options: The MAX1185 is a dual 10-bit ADC, pin-compatible with the MAX1196. Both parts are packaged in a 7mm x 7mm 48-pin TQFP package with exposed paddle. The MAX1192 is an ultra-low-power, miniature dual