APPLICATION NOTE 263

Wafer-Level Chip-Scale Package

Introduction to Chip-Scale Package (CSP)

The packaging technology in the Chip-Scale Package (CSP) enables the integrated circuit to be attached to the printed-circuit board face-down, with the chip's pads connecting to the PC board's pads through individual balls of solder (Figure 1). This technology differs from other ball grid array, leaded, and chip-scale packages because there are no bond wires or interstitial laminates. The principle advantage of the CSP is that the IC-to-PC board inductance is minimized. Secondary benefits are reduction in package size and manufacturing cycle time and enhanced thermal conduction characteristics.

Figure 1. 6x6 CSP

 

CSP Carrier Tape Design (Preliminary)

All CSPs are shipped in tape-and-reel (T&R). CSP tape-and-reel requirements are based on EIA-481 standard. The tape-and-reel construction shown in Figure 2 and Table 1 illustrates minimum requirements and guidelines.

Figure 2. Tape-and-Reel Construction

 

Package Construction

CSP Configurations

CSP
array
Die Size
X/mils
±2mils
Die Size
Y/mils
±2mils
RDL
(Yes/No)
3x2
59
40
No
3x3
59
59
No
4x3
81
59
Yes
4x4
79
79
No
5x4
99
79
No
5x5
99
99
No
6x5
118.5
99
No
6x6
118.5
118.5
No

 


Typical Dimensions

Bump Pitch: 19.7mils/0.5mm
Die Height: 14 ±1mils
Ball Diameter: 12 ±1mils
Die Edge to Center of Corner: 10 ±1mils
Bump Standoff: 9 ±1.5mils
Total Package Height: 22 ±2mils

A detailed description of each CSP package is shown in package drawings available from the Assembly and Packaging Group, Maxim Integrated.

Laser Marking on Backside of the CSP Wafer

 

Table 1. Tape-and-Reel Construction

Constant Dimensions

Tape Size
D0
E1
P0
P2
T1 Max.
G Min.
R Min.
8 mm
&
12mm
1.5
+0.10
1.75±0.10
4.0±0.10
2.0±0.05
0.10
0.75
25
See Note 2,
Table 1
-0.00

Variable Dimensions

Tape Size
E2 Min.
F
W Max.
P1
See Note 4
A0B0
T
8mm
6.25
3.5±0.05
8.3
2.0±0.05
or
4.0±0.10
See
Note 1,
Table 1

1.1mm maximum for
Paper Base Tape,
and
1.6mm maximum for
Non-Paper Base
Compositions.

See Note 2

12mm
10.25
5.5±0.05
12.3
2.0±0.05
or
4.0±0.10
or
8.0±0.10

Notes

1. The cavity defined by A0, B0 and T shall be configured to provide sufficient clearance surrounding the component so that:
  a) the component does not protrude beyond either surface of the carrier tape;
  b) the component can be removed from the cavity in a vertical direction without mechanical restriction after the top cover tape has been removed;
  c) rotation of the component is limited to 20° maximum ( see Sketches A & B);
  d) lateral movement of the component is restricted to 0.05mm maximum (see Sketch C).
2. Tape with or without components shall pass around radius "R" without damage.
3. Bar code labeling (if required) shall be on the side of the reel opposite the sprocket holes. Refer to EIA-556.
4. If P1=2.0mm, the tape may not properly index in all tape feeders.

 

Note: The bumps are facing down in the tape-and-reel carrier. Pin 1 orientation is consistent in each pocket in the carrier tape. Mark layout will have pin 1 ID on top left- hand corner (on the wafer back as shown in Section 2) and a minimum of four product code characters.

 

Printed-Circuit Board Layout

Two types of land patterns are used for surface-mount packages:

1. Solder-Mask Defined (SMD). Pads have solder-mask openings smaller than metal pads.
2. Non-Solder-Mask Defined (NSMD). Metal pads are smaller than solder mask openings.

Better control of the copper etch process, as compared to the solder-mask etch process in the SMD pad definition, makes NSMD preferable. The SMD pad definition introduces stress concentration near the solder-mask overlap region that results in solder joints cracking under extreme fatigue conditions. Smaller pad size in the NSMD definition provides more room for escape routing on the PCB.

The NSMD design was chosen by Maxim during temperature cycle testing. The circular copper pad size should be 10 +2/-0mils and solder-mask openings should be 13 +2/-0mils. The PCB layout assumes 0.1mm (4mils) trace width and 1oz copper layer thickness. Copper pads should be finished with organic solderability preservative coating (OSP). For electroplated nickel-immersion gold-finish pads, the gold thickness must be less than 0.5 micron to avoid making the solder joints brittle.

 

SMT Process Flow

Solder paste deposition using a stencil printing process involves pressurized application of solder paste through predefined apertures. Three general methods exist for stencil fabrication: chemical etching, laser cutting, and nickel plate-up. While all three have advantages in stencil PCB component-attach manufacturing, not all are suitable for generating fine pitch (0.5mm) bump-attach stencils. Chemical etching cannot support the fine geometries and tolerances required for CSP stencils, and is not considered a viable process for producing them.

For laser-cut stencils, a thin stainless-steel foil is held flat while the apertures are cut with a high-powered laser. The observed tight tolerances on aperture dimensions, combined with smooth sidewalls, makes laser cutting stencils a desirable and popular process. However, the cost of laser-cut stencils increases with the number of apertures.

In the nickel plate-up process, the stencil is grown by plating nickel onto a mandrel through a patterned dry-film resist. This process also produces smooth sidewalls with tight shape and size tolerances. However, this process requires patterning and plating equipment that may increase the cost of stencil manufacturing.

The aperture design can be either square or round. In the case of square aperture openings, the corners must have at least a 50-micron radius. Temperature cycling board aperture design from Maxim was square, 10 +2/-0mils in diameter. Stencil thickness was optimized to 5mils. It is recommended to offset apertures from the copper pad to maximize separation between deposited solder paste to avoid bridging.

A Type 3 or finer (no clean) solder paste is recommended.

Component Placement

CSPs can be picked up and placed using standard pick-and-place (P&P) equipment. Minimum requirements of a P&P system include a vision system to recognize and position the part and a mechanical system to perform P&P operations. The placement accuracy of the system is dependent on either its vision system that locates chip edges or on the individual (pre-taught) bump of the CSP. Using the bump as the placement and orientation reference tends to be accurate but is expensive and time consuming.

Both methods are acceptable because during solder reflow, the CSP aligns due to the self-centering feature of the solder joints. The maximum placement offset allowable during assembly is ±0.150mm in the X and Y directions.

Solder Paste Reflow and Cleaning

The following are recommended for high-reliability solder joints resulting from successful solder reflow:

1. Selection of a suitable solder paste. Type 3 or finer (no clean) paste is preferred.
2. Optimized stencil aperture and thickness.
3. Temperature profiling optimization. A thermal profile at specific board locations must be determined. A combination of temperature, reflow oven conveyer speed, and convection flow rate needs to be varied to perform the optimization. During reflow, eutectic solder bumps and paste on the PCB melt in the presence of flux to form a cohesive shiny solder joint. A problematic temperature profile or solder paste will result in "solder balling" (small solder ball formation on solder mask) or semi-reflowed solder paste (signs of solder beads visible).
4. Nitrogen purge is recommended during solder reflow.
5. Level of oxygen is kept low in the reflow chamber at least below 100ppm. A meter incorporated in the furnace will monitor the oxygen level.

CSP packages must not exceed three reflow cycles (at +235°C peak temperature).

Figure 3. Recommended Temperature Profile for Eutectic Solder

Flux cleaning is dependent on the type of flux used in the solder paste. Solder paste with active flux is not recommended due to corrosion issues.

CSP Rework

CSP rework involves the same process as reworking a typical ball-grid array (BGA). Following are the key steps:

1. CSP removal uses localized heating similar to original reflow profile using convection nozzle and preheat from the bottom.
2. Once the nozzle temperature is +190°C, the defective CSP can be removed using tweezers.
3. The pads need to be resurfaced by using a temperature-controlled soldering iron.
4. Gel flux is applied to the pad.
5. A replacement part is picked up using a vacuum needle pick-up tip and placed accurately using a placement jig.
6. Reflow the part using the same convection nozzle and preheat from bottom, matching the original reflow profile.

Solder Joint Inspection

After surface-mount assembly, transmission X-rays can be used for sample monitoring of the solder attachment process to identify defects such as bridging, opens, shorts and voids.

Pack and Ship

Care must be taken in shipping CSPs mounted on PCBs without underfill. The packing specification for CSPs must be reviewed and optimized.

 

Maxim CSP Reliability Data

The Maxim CSP package has been subjected to environmental stress tests similar to the end-user application. These tests include the High-Temperature Operating Life Test, Temperature Humidity Bias Test, Low-Temperature Operating Life Test, Low-Temperature Storage Life Test, and Temperature Cycling Test.

A description of these reliability tests is listed as follows:

High Temperature Operating Life Test

The CSP package is placed in a circuit simulating the end user application, with the CPS device under bias and under accelerated ambient temperature (+70°C, +100°C, +125°C), for an extended time. This test can accelerate failures due to silicon process integrated circuits and bump metal and solder joint reliability unique to CSP technology.

Temperature Humidity Bias Test

This moisture stress test with bias subjects the CSP device to high humidity (85% R.H., 95% R.H.), high temperature (+60°C, +85°C), cycling High/Low temperature, constant bias, or cycling bias. Functional test of the device is performed at the end of the stress test. This test can accelerate electrolytic corrosion and other failures related to silicon process integrated circuits.

Low Temperature Operating Life Test

The CSP device is subjected to simulated life test, in below-normal operating temperatures, to detect any reliability abnormalities not typically revealed.

Low Temperature Storage Life Test

The CSP device is subjected to low-temperature storage environments with no bias applied, to reveal the existence of any weakness in mechanical integrity.

Temperature Cycling Test

The CSP device is subjected to temperature extremes to determine whether changing temperatures affects the device mechanical and electrical integrity. Typical temperature ranges are -35°C/+85°C, -40°C/+100°C, -40°C/+125°C, and -65°C/+150°C.

Table 2 summarizes the reliability test results from the tests performed with 3x3 CSP packages. Tests were conducted with CSP parts mounted onto 4-layer FR4 PCBs. Each assembled FR4 board is then subjected to stress tests as described below. These test results demonstrate that Maxim 3x3 CSP packages can pass all of the stress tests.

Table 2. Maxim CSP Reliability Test Results


RELIABILITY TEST
TEST CONDITIONS
TEST DURATION
RESULTS
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APP 263:
APPLICATION NOTE 263,AN263, AN 263, APP263, Appnote263, Appnote 263