APPLICATION NOTE 14

Design Considerations for All-Silicon Delay Lines


Abstract: This application brief discusses the architectural and structural differences between solid-state and hybrid delay lines. In many cases, solid-state delay lines provide a functional, if not pin-for-pin, replacement for hybrid delay lines at a lower cost, in smaller lighter packages, and with higher reliability. The article outlines the operation of older, modular delay lines and explains how this same functionality is performed using these all-silicon replacements.

Important functional and parametric differences are discussed to give the electronics designer an overview and understanding of silicon delay line technology to simplify the integration into new and existing designs requiring or already using delay line technology.

Silicon Delay Lines vs. Hybrid L-C Networks

Figure 1 shows internal views of a typical 5-tap hybrid delay line and its silicon counterpart. A hybrid is manufactured using a commercially available hex inverter DIP (e.g., 74LS04) with a small PC board placed on top to supply a ground plane. Next, several leads are bent up and over the top of the PC board. Five chip capacitors and a terminating resistor are soldered to the ground plane and a 5-tap ferrite inductor is positioned above. Note that nearly two dozen solder joints are required to electrically connect the various components. Finally, the entire assembly is placed into an oversized plastic tub and filled with a potting material.

Figure 1. Internal views.
Figure 1. Internal views.

By comparison, the silicon delay line consists of a laser-optimized die bonded to a conventional lead frame molded into an auto-insertable industry standard DIP or surface-mount SOIC package. The die is a low-power CMOS design fabricated on 6-inch wafers by Dallas Semiconductor's Class 1 facility. Using lasers for late definition of finished wafers provides both economy and maximum flexibility; both rising and falling edges can be programmed to standard or custom delays over a wide range of values. A post-laser final passivation step protects against contamination by covering the laser fuse windows before packaging.

The basic building block of a silicon delay line consists of a ramp generator with associated logic (Figure 2). The input signal triggers a ramp generator that supplies a laser-adjusted voltage-to-time relationship (Figures 3 and 4). A comparator is used to detect the ramp reaching the reference voltage (VREF); this sets or resets the output latch. The DS1013 family has three independent blocks in parallel while the DS1000, DS1005, and DS1010 families have the blocks connected in series with a single external input (Figure 5). All silicon delay lines, unlike most TTL-based hybrids, have true CMOS output levels.

Figure 2. Basic building block
Figure 2. Basic building block.

Figure 3. Voltage to time conversion.
Figure 3. Voltage to time conversion.

Figure 4. Expanded basic block.
Figure 4. Expanded basic block.

Figure 5. Delay line families.
Figure 5. Delay line families.

The linear ramp generator is implemented with constant current sources charging capacitors (Figure 6). By using a combination of several large current sources and capacitors and binary weighted smaller current sources and capacitors, maximum flexibility with subnanosecond adjustment is obtained on a single silicon die (Figure 7). Under the direction of a computer-controlled tester with 20-picosecond resolution, the proper slope of the ramp (Figure 8) is obtained by directing a laser to remove the unnecessary current sources and capacitors. This is accomplished by opening polysilicon fuses (Figure 9).

Figure 6. Basic ramp generator.
Figure 6. Basic ramp generator.

Figure 7. Laser programmable elements.
Figure 7. Laser programmable elements.

Figure 8. Range of adjustment.
Figure 8. Range of adjustment.

Figure 9. Laser blowing polysilicon fuse.
Figure 9. Laser blowing polysilicon fuse.

Figure 10. Delay vs. temperature.
Figure 10. Delay vs. temperature.

Timing on hybrid lines is determined by coil winding and/or capacitor selection or trimming. Achieving both rising and falling edge accuracy at the same time is difficult and comes at a premium price. Furthermore, timing is subject to the variations of the 74LS04 devices procured from other manufacturers. On silicon delay lines, temperature compensation is implemented by balancing the positive temperature coefficient of the CMOS logic against the negative coefficient of the ramp generator. Figure 10 shows that the logic portion of the circuit, like hybrid delay lines in general, slows linearly with increasing temperature. Since the ramp speeds up nonlinearly, the two effects tend to cancel, minimizing the effects of temperature. Because the net result resembles a parabolic shape, temperature coefficients specified in parts per million (ppm) are inappropriate to describe the behavior of silicon delay lines. A more meaningful parameter is maximum shift from nominal anywhere over the rated temperature range. Figure 11 compares the two technologies over temperature. While some silicon delay line families (DS1000 and DS1010) provide minimal voltage independence (4% delay change for 5% supply variation), the newer designs (DS1005 and DS1013) provide a higher degree of supply isolation (= < 1% delay change for 5% supply variation). The newer designs achieve supply voltage independence by employing positive ramps referenced to ground rather than negative ramps referenced to VCC (Figure 12).

Figure 11. Hybrid vs. silicon over temperature.
Figure 11. Hybrid vs. silicon over temperature.

Figure 12. Comparison of delay designs.
Figure 12. Comparison of delay designs.

While hybrids offer little flexibility in packaging, silicon lines are available in a variety of industry standard DIP and SOIC packages (See Packaging Options below). To maintain compatibility with existing designs based on hybrids having missing pins, a clipped lead version is offered. Finally, for surface mount applications, two solutions are available: 300mil DIPs with the leads trimmed and "gull winged," and industry standard SOIC packages.

Table 1 summarizes some of the disadvantages of the hybrid design and some of the advantages of the silicon solution.

Table 1.
Disadvantage of Hybrids Advantages of Silicon
  • Unreliable solder joints
  • Difficult to control falling edge accuracy
  • TTL output levels
  • Large, non-standard package dimensions
  • Reliable all-silicon design
  • Accurate rise and fall edges
  • Easily customized
  • CMOS output levels
  • No inductors
  • Industry standard DIP and SOIC packaging
  • Standard IC handling including reflow soldering

  • Package Options

    Dual-In-Line (DIP)

    DIP packages are available in pin counts of 8, 14 and 16 pins. Three lead-forming options are available:

    Straight lead:
    This is the conventional package and is used for through-hole mounting in PCBs.

    Gullwing:
    The leads are formed to sit flat on the surface of a PCB for surface mount applications.

    Sheared NC
    All "no connect" (NC) leads are sheared off the package. This package is commonly used for hybrid replacement applications.

    Note:
    The use of gullwing or sheared NC packages is not encouraged for new designs; however, these packages will continue to be made available for existing designs.

    Small Outline (SOIC)

    Small outline surface mount packages are available in pin counts of 8, 14 and 16 pins. Two package widths are also available: 150mil and 300mil.

    Package Availability / Letter Designations
    # Pins DIP SOIC
    STD Gullwing Sheared 150mil 300mil
    8 M H   Z  
    14 none* G K R  
    16         S
    * Default package, no letter designator required.
    Tape and reel packaging is also available; contact the factory for more information.


    Frequently Asked Questions

    How do silicon timed delays differ from hybrid devices?

    A typical hybrid consists of a hex inverter DIP, a PC board acting as a ground plane plus chip capacitors, a terminating resistor and a multiple tap ferrite inductor. Timing is determined by coil winding and/or capacitor selection or trimming. The Dallas Semiconductor Silicon Timed Circuit (STC) design uses a laser-optimized die bonded to a conventional lead frame molded into an auto-insertable DIP or SOIC package.

    What are the advantages of silicon timed circuits over hybrid devices?

    STCs offer advantages in design, packaging and manufacture over hybrids. Specifically, STCs offer the increased reliability of silicon and greater accuracy on both rise and fall edges. Unlike TTL devices, STCs are CMOS devices and offer true output levels. Using standard DIP and SOIC packaging, STCs are well suited to standard IC handling including reflow soldering.

    What is the basic operation of a silicon delay line device?

    The basic building block of the silicon delay line is a ramp generator and associated logic. The input signal triggers a ramp generator that supplies a laser-adjusted voltage-to-time relationship.

    Is there a way to correlate the performance of silicon time delays against hybrids?

    Following this procedure will provide a correlation. At fast (3ns) rise/fall input pulses with 0/3 volt logic levels, low inductance decoupling techniques using 0.01 to 0.1 µF capacitors, with low capacitance measurement probes placed as close as possible to the package and relaxed timing (500ns pulse width, 1µs period), will aid in timing correlation when measured at 1.5-volt levels.

    How does laser adjustment time the delay?

    Under the direction of a computer-controlled tester with 20-picosecond resolution, the proper slope of the ramp is obtained by directing a laser to open polysilicon fuses, removing unnecessary current sources and capacitors.

    Can I get any delay time I need?

    Yes, silicon delay lines can be customized to meet your design timing requirements. We can even supply sample quantities in ceramic packages for evaluation.

    Do STCs need to compensate for temperature like hybrids?

    On silicon delay lines, temperature compensation is implemented by balancing the positive temperature coefficient of the CMOS logic against the negative coefficient of the ramp generator. The logic portion of the circuit speeds up linearly with increasing temperature while the ramp speeds up non- linearly. These two effects tend to cancel, minimizing the effects of temperature. Rather than measuring the coefficients in parts per million, silicon delay lines are meaningfully measured as the maximum shift from nominal anywhere along the rated temperature range.

    Do silicon timed delays require decoupling?:

    STCs contain noise sensitive voltage detection circuits and fast rise time output circuits, so decoupling is indicated. A 0.01 to 0.1 µF low inductance capacitor should be used in close proximity to the delay line to assure the highest performance.

    Do silicon delay lines also function as glitch discriminators?

    Yes. If a pulse or glitch is less than about 60% of the first stage delay of a 5- or 10-tap serial device (DS1000, DS1005 or DS1010) or less than about 60% of any tap on a 3-in-1 parallel device (DS1013), there will be no output.

    Can a silicon delay line be used to time-shift a square wave?

    Yes, it is a good solution. Just be certain the period specification is met.

    What temperature parameters do silicon timed delays meet?

    STCs function over the full military (-55°C to +125°C) temperature range, yet have been optimized for the commercial (0°C to +70°C) range. One product family, the DS1000-IND, is available in the industrial temperature range. Other parts may be specified for the industrial temperature range on a custom basis.

    Can I add or daisy chain several devices to achieve a longer delay?

    Daisy chaining silicon delay lines presents a problem that is increased with the number of packages in a chain. A voltage chopped stabilization circuit in the design causes a slight time jitter (well within specifications and almost transparent to the circuit) on the output. When packages are daisy chained, the time jitter is cumulative and degrades the accuracy of downline stages. If four to six packages are chained in a series, the results are generally unacceptable.

    What about daisy chaining the stages of a parallel STC?

    Some jitter will be added with each stage when added in a series. This will not be a problem in most cases. Users report that daisy chaining this way is a convenient method of implementing non standard series delays.

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