MAX3670: Loop-Filter Configuration for the MAX3670 Low-Jitter PLL Reference Clock Generator
Errors
APPLICATION NOTE 1032
MAX3670: Loop-Filter Configuration for the MAX3670 Low-Jitter PLL Reference Clock Generator
Abstract:The MAX3670 low-jitter clock generator is a monolithic phase-locked loop (PLL) that uses an externalhigh-Q voltage-controlled oscillator (VCO) to create a very low jitter clock signal phase-locked to a systemclock input. It is ideal for SONET OC-48 or OC-192 applications requiring a very low jitter 156 MHZ or 622MHz clock signal. When used with a low-jitter voltage-controlled SAW oscillator (VCSO) or avoltage-controlled crystal oscillator (VCX), the total system jitter can be less than 1 psrms. This designnote provides analysis and examples that address optimal PLL configuration, including externalcomponent values, internal divider settings, and internal phase detector gain for low-jitter applications.
Next Steps
EE-Mail
Subscribe to EE-Mail and receive automatic notice of new documents in your areas of interest.
The content on this webpage is protected by copyright laws of the United States and of foreign countries. For requests to copy this content, contact us.
Thank You for interest in Maxim Integrated. Our free samples program limits the quantities that we can provide to each customer per calendar year.If you feel that you have received this message in error, please contact samples-admin@maximintegrated.com. Please click here to place an order.