The MAXREFDES74# reference design performs high-speed, 18-bit, precision data acquisition based on Maxim’s leading-edge, high-accuracy, low-power data converters. The MAXREFDES74# design works as a building block for a high-speed, low-power, high-accuracy data acquisition and control system for industrial process control and automation, and high-speed protection systems for power distribution and automation. By changing the ADC and DAC to pin-compatible 16-bit devices such as the MAX11166 and the MAX5316, a 16-bit data acquisition system can also be tested.
The MAXREFDES74# reference design features:
MAX11156
MAX5318
The MAXREFDES74# reference design performs high-speed, 18-bit, precision data acquisition based on Maxim’s leading-edge, high-accuracy, low-power data converters. The MAXREFDES74# design works as a building block for a high-speed, low-power, high-accuracy data acquisition and control system for industrial process control and automation, and high-speed protection systems for power distribution and automation. By changing the ADC and DAC to pin-compatible 16-bit devices such as the MAX11166 and the MAX5316, a 16-bit data acquisition system can also be tested.
The MAXREFDES74# reference design features:
MAX11156
MAX5318
The block diagram of the MAXREFDES74# board is shown in Figure 1.
Figure 1. MAXREFDES74# block diagram.
The analog front-end consists of two user-selectable MAX9632 op amps, followed by the MAX11156. The op amps can be configured as inverting or noninverting amplifiers by jumper selectors. Both op amps work as anti-aliasing lowpass filters (LPF) and can be daisy-chained to create a second-order LPF.
The output of the MAX5318 DAC can also be configured as a positive or negative single-ended output, or as a true differential output through three MAX9632 op amps. The DAC output can also be shifted up to double the output level to 2 x VREF.
The voltage reference (VREF) for both the ADC and DAC comes from the selectable reference sources, which include the MAX6126, with 3ppm/°C, 0.02% initial accuracy VREF in an 8-pin SO package, and the MAX6070, with 6ppm/°C, 0.04% initial accuracy VREF in a 6-pin SOT23 package. The MAX11156 can use an internal VREF (default operation) or one of the external references.
The shunt positions for major ADC configurations are shown in Table 1 and Figure 2, and for the DAC output in Table 2, and a VREF connection in Table 3.
Table 1. ADC Input Configuration
CONFIG # | ADC INPUT CONFIGURATION | INPUT CONNECTORS | SHUNT POSITIONS |
---|---|---|---|
1 | Noninverting, single-ended, second-order LPF (default) | CON3: AIN0+ or (TP2 and TP8): AIN0+ and AGND | J28: 1-2 J29: 1-2 and 3-4 J32: 5-6 and 3-4 J10: 1-2 and 9-10 |
2 | Noninverting, differential, second-order LPF | CON3 (TP2): AIN0+ CON2 (TP1): AIN0- |
J28: Open J29: 1-2 J32: 5-6 and 3-4 J10: 1-2 and 9-10 |
3 | Inverting, single-ended, second-order LPF | CON2: AIN0 or (TP1 and TP8): AIN0 and AGND |
J28: 3-4 J29: 3-4 J32: 1-2 and 7-8 J10: 1-2 and 9-10 |
4 | Inverting, differential, second-order LPF | CON2 (TP1): AIN0- CON3 (TP2): AIN0+ |
J28: Open J29: 3-4 J32: 1-2 and 7-8 J10: 1-2 and 9-10 |
5 | Noninverting, single-ended, first-order LPF | CON5: AIN1 or (TP7 and TP15): AIN1 and AGND |
J29: 1-2 J32: 3-4 and 7-8 J10: 1-2 and 9-10 |
6 | Differential, first-order LPF | CON5 (TP7): AIN1+ CON4 (TP10): AIN1- |
J29: Open J32: 3-4 and 7-8 J10: 1-2 and 9-10 |
7 | Inverting, single-ended, first-order LPF | CON4: AIN1 or (TP10 and TP15): AIN1 and AGND | J29: 3-4 J32: 1-2 and 7-8 J10: 1-2 and 9-10 |
8 | DAC noninverting, single-ended | Use the on-board MAX5318 as input source* | J10: 3-4 and 9-10 J9: 1-2 J5: 1-2 J18: 1-2 |
9 | DAC inverting, single-ended | Use the on-board MAX5318 as input source* | J10: 5-6 and 9-10 J9: 1-2 J5: 1-2 J18: 1-2 |
DAC differential | Use the on-board MAX5318 as input source* | J10: 3-4 Jump wire J10: 5-10 |
*DAC output configuration must be compliant with the ADC input range.
Table 2. DAC Output Configuration
CONFIG # | DAC OUTPUT | SHUNT POSITIONS | OUTPUT CONNECTORS |
---|---|---|---|
10 | Single ended, 0 to 3 x VREF | J9: 1-2 J5: 1-2 J18: 1-2 |
CON11: DAC_OUT+ or (TP46 and TP41): DAC_OUT+ and AGND |
11 | Single ended, 0 to -3 x VREF | J9: 1-2 J5: 1-2 J18: 1-2 |
CON10: DAC_OUT- or (TP18 and TP17): DAC_OUT- and AGND |
12 | Differential, - 3 x VREF to 3 x VREF |
J9: 1-2 J5: 1-2 J18: 1-2 |
CON11 (TP46): DAC_OUT+ CON10 (TP18): DAC_OUT- |
13 | Single ended, -1.5 x VREF to 1.5 x VREF (default) | J9: 3-4 J5: 1-2 J18: 1-2 |
CON11: DAC_OUT+ or (TP46 and TP41): DAC_OUT+ and AGND |
Note: Alternate connections are shown in parentheses.
Table 3. VREF Connection
CONFIG # | VREF | SHUNT POSITIONS FOR ADC | SHUNT POSITIONS FOR DAC |
---|---|---|---|
14 | Internal | J13: open (default) | — |
15 | External U11 (MAX6126) | J13: 2-3 | J7: 2-3 (default) |
16 | External U12 (MAX6070) | J13: 1-2 | J7: 1-2 |
Figure 2. Default shunt positions.
The MAXREFDES74# board receives power from a single DC source of 15V to 20V, 300mA through a J1 power jack. The MAX13256, H-bridge driver and transformer create an additional negative rail for +20V and -20V. The power is then rectified and regulated down to a +15V and -15V supplies for the op amps, as well as into +5V VDD and 3.3V VDDIO for VREF, ADC, and DAC. See the MAXREFDES74# schematic for details. Specific voltages may be connected to the board for each rail, see Table 4 for corresponding shunt positions.
Table 4. Power Supply to the Board
POWER | INPUT CONNECTORS | SHUNT POSITIONS |
---|---|---|
Single +15V to +20V input from a wall adapter (default) | J1 | J30: 1-2 Enable U1 J15: 3-4 J16: 3-4 J17: 3-4 J24: 5-6 |
An external ±20V | TP35 (+20V) TP30 (-20V) TP36 (Common 0V) |
J30: 2-3 Disable U1 J15: 1-2 J16: 1-2 J17: 3-4 J24: 5-6 |
An external ±15V | TP9 (+15V) TP23 (-15V) TP22 (Common 0V) |
J30: 2-3 Disable U1 J15: 1-2 J16: 1-2 J17: 1-2 J24: 3-4 |
The MAXREFDES74# board is connected to the ZedBoard through a low-pin-count FMC CON1 connector. The ZedBoard should be connected to a PC through an Ethernet port, which allows the GUI to perform different operations with full control over mezzanine card functions.
Required Equipment
Procedure
The MAXREFDES74# board is fully assembled and tested. Follow the steps below to verify board operation:
MIO6 | GND |
MIO5 | 3V3 |
MIO4 | 3V3 |
MIO3 | GND |
MIO2 | GND |
Figure 3. MAXREFDES74# GUI.
Figure 4. DMM tab.
Figure 5. Scope tab.
Figure 6. Histogram tab.
Figure 7. FFT tab.
Figure 8. Coherent sampling of a 10kHz sine wave.
Figure 9. Coherent sampling of a 1kHz sine wave.
Note: The DAC output on TP54 is in the range from 0V to VREF (4.096V), but on TP46 it can be from -1.5 x VREF (-6.1V) to 3 x VREF (+12.3V), and on TP18 from +6.1V to -12.3V, see Table 2. Alternatively, the DAC code can be entered in hex format in the DIN box and set by clicking the Write button.
By pressing the Generate button, the software calculates the necessary points and creates a lookup table (LUT) in the ZedBoard FPGA’s RAM. FPGA will loop around the LUT to generate a continuous waveform. Use an oscilloscope to check the output waveform. The output can be disabled by clicking on the Stop button.
The user can generate a waveform produced by the MAX5318 DAC and analyze it using the on-board MAX11156 ADC, since the DAC and ADC work independently from each other.
Figure 10. Scope of the sine wave in closed-loop operation.
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ZedBoard is a trademark of ZedBoard.org.
Zynq is a registered trademark of Xilinx, Inc.
Required Equipment
Hardware Files:
Schematic
Bill of Materials (BOM)
PCB Layout
PCB Gerber
Software Files:
Software GUI
Firmware Files:
ZedBoard Firmware