#### Introduction

To a large degree, the reliability of a 1-Wire network depends on the characteristics of the driver circuit that the host computer uses to communicate with 1-Wire slave devices. This document describes a 1-Wire master interface that uses careful impedance matching and an "intelligent" (software-controlled) strong pullup to accomplish reliable operation in networks from very lightweight to very heavy, up to 500m equivalent size. For guidelines on how to create reliable 1-Wire networks see tutorial 148, "Guidelines for Reliable Long Line 1-Wire Networks".

#### Introduction

To a large degree, the reliability of a 1-Wire network depends on the characteristics of the driver circuit that the host computer uses to communicate with 1-Wire slave devices. This document describes a 1-Wire master interface that uses careful impedance matching and an "intelligent" (software-controlled) strong pullup to accomplish reliable operation in networks from very lightweight to very heavy, up to 500m equivalent size. For guidelines on how to create reliable 1-Wire networks see tutorial 148, "Guidelines for Reliable Long Line 1-Wire Networks".

#### Circuit Description

The network driver (Figure 1) consists of a pulldown section (Q1, R1, C1, R5) and a pullup section (Q2, R2, C2, R6). A third transistor and surrounding components (Q3, C4, R7) form a strong pullup section to supply extra power for devices such as EEPROMs, or temperature sensors. This "strong-pullup" function is not discussed in this document. Of the three transistors, a maximum of one is conducting at any time. When there is no 1-Wire communication ("idle" state), all three transistors are nonconducting.

Figure 1. Driver schematic.

The series path of R4, R1, and R3 provides the standard 1-Wire pullup to VCC. With this circuit, the total pullup resistance is approximately 1kΩ. This value applies when the 1-Wire line is idle. Since R4 is connected to the drain of Q1, the current flowing through it when Q1 is conducting does not affect the lowlevel voltage on the 1-Wire line. R4 + R1 + R3 together with the load or "weight" of the 1-Wire network determine the speed at which the voltage on the 1-Wire rises to 5V. Lowering R4 is not recommended since it raises the low-level voltage on the 1-Wire, which is undesirable. The Schottky diodes D1 and D2 eliminate spikes from electrostatic discharge (ESD) hits or cross coupling from other cabling nearby by conducting them to GND and VCC, respectively. R3 limits the ESD current and protects D1 and D2.

A special characteristic of this driver is the proper line termination of the 1-Wire cable on the master end. The category 5 unshielded twisted-pair data cable, which is recommended for 1-Wire applications, has a characteristic impedance of approximately 100Ω. Line termination is accomplished through R1 or R2 in series with R3 when Q1 or Q2 is conducting. C3 in series with R1 and R3 provide an AC-coupled termination for presence pulses. To adapt this driver to a different impedance, R1 and R2 need to be changed accordingly.

All three sections of this driver are slew-rate controlled when the associated transistor is turned on. R5 and C1 limit the slew rate when the driver pulls the 1-Wire line low, e.g., at the beginning of a time slot or a reset pulse. R6 and C2 limit the slew rate when the dynamic pullup becomes active. R7 and C4 limit the slew rate of the active pullup. The time constant of all three sections is 0.5µs. This value results in a slew rate of approximately 4V/µs. For details and scope traces see the Performance Examples section.

#### Circuit Operation

Disregarding the strong pullup circuitry (Q3, R7, C4) the driver requires three connections to a supervising microcontroller. These signals are called DRIVE, DPU, and SENSE. DRIVE is an active-high signal that initiates 1-Wire communication by turning on Q1. DPU is an active-low signal that activates the dynamic pullup Q2. SENSE is essentially a through-connection from the 1-Wire line to an input port of the microcontroller. 1-Wire ground and driver/microcontroller GND are the same. To perform 1-Wire communication it is necessary to properly generate the DRIVE and DPU signals and to read from the 1-Wire line through the SENSE input at the appropriate times. 1-Wire communication knows four cases of waveforms; these are reset/presence-detect sequence, and the three cases of communication time slots.

##### Reset Presence and Detect

All 1-Wire communication begins with a reset pulse followed by a window for the presence pulse. Figure 2 shows the 1-Wire waveform. To generate the reset pulse, the DRIVE signal is activated for a duration from A to B (see Figure 2). Starting at A, the voltage on the 1-Wire ramps down to 0V. As DRIVE gets inactive at B, the voltage on the 1-Wire starts rising, unless a 1-Wire device pulls the line low to signal an interrupt condition (see DS1904 and DS2417 data sheets, Type 2 Interrupt). To properly accommodate this interrupt case, the status of the 1-Wire is sampled repeatedly starting at C until the 1-Wire has reached a logic high level at D. Shortly after D, the dynamic pullup DPU is activated (point E). This quickly pulls the 1-Wire line to 5V. At F the dynamic pullup ends. Assuming that a 1-Wire device is present, it generates a presence pulse, which begins at G and ends at I. At H, somewhere between G and I, the status on the 1-Wire is sampled to test whether a 1-Wire device is present. As the presence pulse ends, the voltage on the 1-Wire starts rising towards 5V. At J the logic status of the 1-Wire is sampled again to detect whether a Type 1A interrupt (see DS1904/DS2417 data sheets) is signaled. Without interrupt, the logic state is high, as shown in Figure 2, and the dynamic pullup is activated again from K to L, which ensures that the 1-Wire line is fully recharged. With interrupt signal, the status sensed at J is a logic zero and another series of repeated sampling, exactly like that at the end of the reset pulse is necessary (i.e., going back to C and continue sampling). The interrupt pulse is understood as a reset pulse by other 1-Wire devices. Therefore they generate a presence pulse as the response, except for the interrupting device (i. e., when J is reached in the second pass, the logic status of the 1-Wire is high, as shown in Figure 2. In any case, the reset/presence-detect sequence ends at M, where a time slot begins.

Figure 2. Reset and presence-detect sequence.

A to B B to C D to E E to F E to H H to J J to K K to L L to M Table 1. Recommended Timing Values for Reset/Presence Detect Sequence 480µs 0 to 2µs 0 to 2µs 8µs 72µs 240µs 0 to 2µs 60µs > 2µs

The sampling point H must be chosen to hit the presence pulse window, which is determined by the timing spread between the fastest and the slowest 1-Wire device present. Data sheets specify this window as tMSP. The timing reference for tMSP begins when the 1-Wire device detects logic-HIGH level after the reset pulse is over. In Figure 2 this reference point approximately coincides with E. The duration from A to C is equivalent to the sum of tF (fall time) and tRSTL (reset low time). In case of a Type 2 interrupt, the effective reset low time is the sum of A to B and the duration of the interrupt pulse (see DS1904 and DS2417 data sheets). The time from E to M is called reset high time tRSTH. Data sheets specify tRSTL and indicate how to determine the minimum duration of tRSTH. There is no maximum for tRSTH.

#### Communication Time Slots

##### Write Zero Time Slot

The write zero time slot transmits a 0-bit on the 1-Wire line. Figure 3 shows the 1-Wire waveform. To generate the write zero time slot, the DRIVE signal is activated for a duration from A to B0. Starting at A, the voltage on the 1-Wire ramps down to 0V. As DRIVE becomes inactive at B0, the voltage on the 1-Wire line starts rising. Shortly after B0, the dynamic pullup DPU is activated (point C0). This quickly pulls the 1-Wire line to 5V. At D0 the dynamic pullup ends. The next time slot or a reset/presence-detect sequence may follow at E0.

Figure 3. Write zero time slot.

A write zero time slot does not require sampling the data line. Therefore Figure 3 does not show any sampling point. However, it is definitely permissible to sample the 1-Wire line at the same point in time as with a read time slot (Figure 4 or 5). The sampled logic state is always 0, indicating that the circuit actually writes a 0 to the 1-Wire line. The duration from A to C0 is equivalent to the sum of tF (fall time) and tW0L (write zero low time). The time from C0 to E0 is called recovery time tREC. Data sheets specify tW0L and a minimum value for tREC. The time from A to E0 is also referred to as time slot duration tSLOT.

A to B0 B0 to C0 C0 to D0 A to E0 Table 2. Recommended Timing Values for Write Zero Time Slot 60µs 2µs 16µs 80µs

The write one time slot transmits a 1-bit on the 1-Wire line. Figure 4 shows the 1-Wire waveform. Reading a 1-bit from the 1-Wire line results in exactly the same waveform as writing a 1-bit. Therefore, the write one and read one case are combined and discussed as a single case. To generate the write one or read time slot, the DRIVE signal is activated for a duration from A to BR. Starting at A, the voltage on the 1-Wire ramps down to 0V. As DRIVE becomes inactive at BR, in the case of reading or writing a 1-bit, the voltage on the 1-Wire line starts rising. At CR the status on the 1-Wire is sampled. Since the bit read is a 1, the dynamic pullup is activated immediately, lasting from D1 to E1. This quickly pulls the 1-Wire line to 5V. The next time slot or a reset/presence-detect sequence may begin at F1.

The sampling point CR must be chosen to hit the master sampling window, which is determined by the timing of the fastest 1-Wire device. In data sheets this window is called tMSR. The timing reference for tMSR begins when the 1-Wire device detects a logic LOW-level after the beginning of the time slot. In Figure 4 this reference point is approximately A plus fall time tF. The duration from A to BR is equivalent to the sum of tF (fall time) and tRL (read low time). Data sheets specify tRL (equal to tW1L) and tMSR. The time from A to F1 is also referred to as time slot duration tSLOT.

A to BR A to CR CR to D1 D1 to E1 A to F1 Table 3. Recommended Timing Values for Write One/Read Time Slot (Read One) 9µs 18µs 0 to 2µs 60µs 80µs

The read zero time slot is a read time slot that reads a 0-bit from the 1-Wire line. Figure 5 shows the 1-Wire waveform. To generate the read time slot, the DRIVE signal is activated for a duration from A to BR. Starting at A, the voltage on the 1-Wire ramps down to 0V. To send a 0-bit, a 1-Wire device starts pulling the 1-Wire line low after A but before BR. The voltage on the 1-Wire line, therefore, is first driven low by the 1-Wire master and then remains held at a logic low by one or more 1-Wire devices. When BR has occurred, the master pulldown is turned off. At CR the status on the 1-Wire is sampled. Since the bit read is a 0, the 1-Wire is sampled repeatedly. At D0 the 1-Wire device stops pulling the line low, which allows the voltage to rise. A subsequent sampling at E0 determines that the line has reached a logic-high level. Now the dynamic pullup is activated, lasting from F0 to G0. This quickly pulls the 1-Wire line to 5V. The next time slot or a reset/presence-detect sequence may begin at H0.

The sampling point CR is the same as with the write one/read time slot. The distance between the subsequent sampling points should be as short as the microcontroller and software allow. The time from A to H0 is also referred to as time slot duration tSLOT.

A to BR A to CR E0 to F0 CR to G0 A to H0 Table 4. Recommended Timing Values for Read Time Slot (Read Zero) 9µs 18µs 0 to 2µs 60µs 82µs

#### Practical Considerations

The structure of the signals that control the advanced 1-Wire network driver is relatively complex. The algorithms, however, are straightforward. For this reason, this driver is typically implemented in software, using a microcontroller that is fast enough to generate the signals in real-time. The flow charts given below assist in implementing the advanced driver using any suitable microcontroller that the user is familiar with. The execution time of every command at the user-specified crystal frequency must be taken into account to generate the proper timing.

#### Software Flow Charts

Note 1: Decrementing is necessary only if the timer is implemented as a counter rather than a real timer. The timer should expire after 5000µs.

Note 2: Presence and Short are logical variables that report to the superordinated program the result of the reset/presence-detect sequence. Interrupt is not reported as a variable since there is only one 1-Wire chip that can generate interrupts (DS1904 and DS2417) and the use of interrupts can considerably reduce the effective speed of a 1-Wire network.

This flow chart assumes that there is a logical input variable that controls whether to generate a write zero or read time slot. The write one time slot is the same as a read time slot. The bit variable BitValue reports the result of the time slot to the superordinated program.

Note 1: Decrementing is necessary only if the timer is implemented as a counter rather than a real timer. The timer should expire after 45µs.

Note 2: According to the flow chart, DPU is repeatedly activated before the timer expires. This is acceptable since activating a signal that is already active does not change the state of that signal. If desired, one can test whether DPU is already active, and if so, not activate it again while performing the loop.

#### Performance Examples

The scope traces on the next page show 1-Wire signals generated by the driver as described in this document. When verifying the signals, especially at the far end of a cable, it is necessary to use a differential probe, leaving the probe's ground reference floating. Otherwise the probe's ground connection would bypass the 1-Wire ground reference and change the topology of the system. If a differential probe is not available, one must isolate the oscilloscope-ground from mains-ground through a transformer or use a battery-operated oscilloscope. Alternatively one could disconnect the safety ground of the oscilloscope's power-supply cable.

##### Scope Traces

Reset/Presence Detect Sequence (as in Figure 2).

Write Zero Time Slot (as in Figure 3).

Write One/Read One Time Slot (as in Figure 4).

Read Zero Time Slot (as in Figure 5).

Falling edge at the far end of a 300m cable.

Same edge seen at the near end of the 300m cable.

Note: A product similar to the Advanced 1-Wire Line Driver is manufactured by Southwind Enterprises. See http://ibuttonlink.com/ for technical details and ordering information.

Status:
Package:
Temperature:

#### Parts Used

• Unique 1-Wire Interface Requires Only One Port Pin for Communication
• Derives Power from Data Line (Parasite Power); No Local Power Supply Needed
• Multidrop Capability Simplifies Distributed Temperature-Sensing Applications

• Unique 1-Wire Interface Requires Only One Port Pin for Communication
• Each Device has a Unique 64-Bit Serial Code Stored in On-Board ROM
• Multidrop Capability Simplifies Distributed Temperature-Sensing Applications

• Unique 1-Wire Interface Requires Only One Port Pin for Communication
• Integrated Temperature Sensor and EEPROM Reduce Component Count
• Multidrop Capability Simplifies Multisensor Systems

• High Accuracy, Full-Featured Digital Temperature Logger Simplifies Temperature Data Collection and Dissemination of Electronic Temperature Record
• Rugged Construction Survives Harsh Environments
• Simple Serial Port Interfaces to Most Microcontrollers for Rapid Data Transfer

• 4096 bits of Read/Write Nonvolatile Memory
• 256-bit Scratchpad Ensures Integrity of Data Transfer
• Memory Partitioned into 256-bit Pages for Packetizing Data

• Unique 1-Wire® Interface Requires Only One Port Pin for Communication
• Maximize System Accuracy in Broad Range of Thermal Management Applications
• Parasite Power Mode Requires Only 2 Pins for Operation (DQ and GND)

• 1128 bits of 5V EEPROM memory partitioned into four pages of 256 bits, a 64-bit write-only secret and up to five general purpose read/write registers
• Write access requires knowledge of the secret and the capability of computing and transmitting a 160-bit MAC as authorization
• Secret and data memory can be write-protected (all or page 0 only) or put in EPROM-emulation mode ("write to 0", page 1)
Common iButton Features
• Unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit CRC tester) assures absolute traceability because no two parts are alike
• Multidrop controller for 1-Wire net
• Digital identification and information by momentary contact

• 4096 Bits Electrically Erasable Programmable Read-Only Memory (EEPROM)
• Unique, Factory-Lasered and Tested 64-Bit Registration Number (8-Bit Family Code + 48-Bit Serial Number + 8-Bit CRC Tester) Assures Absolute Identity Because No Two Parts Are Alike
• Built-In Multidrop Controller Ensures Compatibility with Other MicroLAN Products

• Unique 1-Wire® Interface Requires Only One Port Pin for Communications
• Reduced Component Count with Integrated Temperature Sensor and Interface
• Simplifies Distributed Temperature Sensing with Multidrop Capability

• Guaranteed Unique 64-Bit ROM ID Chip for Absolute Traceability
• Minimalist 1-Wire® Interface Lowers Cost and Interface Complexity
• Wide Voltage and Temperature Operating Ranges Enables Robust System Performance

• Digital thermometer measures temperature 1/8°C increments with ±1°C accuracy
• Built-in real-time clock (RTC) and timer has accuracy of ±2 minutes per month from 0°C to 45°C
• Water resistant or waterproof if placed inside DS9107 iButton capsule (Exceeds Water Resistant 3 ATM requirements)
Common iButton Features
• Digital identification and information by momentary contact
• Unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit CRC tester) assures absolute traceability because no two parts are alike
• Multidrop controller for 1-Wire net

• Digital thermometer measures temperature 1/8°C increments with ±1°C accuracy
• Built-in real-time clock (RTC) and timer has accuracy of ±2 minutes per month from 0°C to 45°C
• Water resistant or waterproof if placed inside DS9107 iButton capsule (Exceeds Water Resistant 3 ATM requirements)
Common iButton Features
• Digital identification and information by momentary contact
• Unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit CRC tester) assures absolute traceability because no two parts are alike
• Multidrop controller for 1-Wire net

• Unique 1-Wire Interface Requires Only One Port Pin for Communication
• Derives Power from Data Line ("Parasite Power")Does Not Need a Local Power Supply
• Multi-Drop Capability Simplifies Distributed Temperature Sensing Applications

• Unique 1-Wire Interface Requires Only One Port Pin for Communication
• Derives Power from Data Line ("Parasite Power")Does Not Need a Local Power Supply
• Multi-Drop Capability Simplifies Distributed Temperature Sensing Applications

• Unique 1-Wire® Interface Requires Only One Port Pin for Communication
• Reduce Component Count with Integrated Temperature Sensor and EEPROM
• Parasitic Power Mode Requires Only 2 Pins for Operation (DQ and GND)

• 1128 Bits of 5V EEPROM Memory Partitioned Into Four Pages of 256 Bits, a 64-Bit Write-Only Secret, and Up to Five General-Purpose Read/Write Registers
• On-Chip 512-Bit ISO/IEC 10118-3 SHA-1 Engine to Compute 160-Bit Message Authentication Codes (MACs) and to Generate Secrets
• Write Access Requires Knowledge of the Secret and the Capability of Computing and Transmitting a 160-Bit MAC as Authorization

• 16384 bits Electrically Programmable Read Only Memory (EPROM) communicates with the economy of one signal plus ground
• Unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit CRC tester) assures absolute traceability because no two parts are alike
• Built-in multidrop controller ensures compatibility with other 1-Wire Net products

• Four high-impedance inputs to measure analog voltages over the 1-Wire bus
• User programmable input range (2.56V, 5.12V), resolution (1 to 16 bits) and alarm thresholds
• 5V, single supply operation

• 4096 bits of nonvolatile dual-port memory including real-time clock/calendar in binary format, programmable interval timer, and programmable power-on cycle counter
• 1-Wire interface for communication at 16.3kbps
• 3-wire host interface for high-speed data communications at 2Mb/s

• 65,536 bits electrically programmable read only memory (EPROM)
• Unique, factory-lasered and tested 64-bit registration number assures absolute traceability because no two parts are alike
• Built-in multidrop controller ensures compatibility with other 1-Wire products
Special Features
• 4096 bits of read/write nonvolatile (NV) memory organized as 16 pages of 256 bits each
• Eight memory pages with individual 64-bit secrets and 32-bit read-only nonrolling-over page write-cycle counters
• Secrets are write-only and have their own individual write-cycle counters
Common iButton Features
• Unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit CRC tester) assures absolute traceability because no two parts are alike
• Multidrop controller for MicroLAN
• Digital identification and information by momentary contact

• 4096 bits Electrically Erasable Programmable Read Only Memory (EEPROM)
• Overdrive mode boosts communication speed to 142kbps
• 256-bit scratchpad ensures integrity of data transfer

• Real-Time Clock/calendar in binary format
• Uses the same binary time/date representation as the DS1994 but with 1 second resolution
• Clock accuracy is better than ±2 minutes per month at 25°C

• Real-time clock with 1-Wire interface
• Uses the same binary time/date representation as the DS2404 but with 1 second resolution
• Clock accuracy ±2 minutes per month at 25°C

• 1024 bits Electrically Programmable Read-Only Memory (EPROM) communicates with the economy of one signal plus ground
• EPROM partitioned into four 256-bit pages for randomly accessing packetized data
• Each memory page can be permanently write-protected to prevent tampering

• 65536 bits Electrically Programmable Read Only Memory (EPROM) communicates with the economy of one signal plus ground
• Overdrive mode boosts communication speed to 142 kbits per second
• EPROM partitioned into two hundred and 56 256-bit pages for randomly accessing packetized data records

• 1024 bits or 64kbits electrically programmable read only memory (EPROM) communicates with the economy of one signal plus ground
• Unique, factory lasered and tested 64-bit registration number (8-bit family code, 36-bit serialization, 12-bit UniqueWare identifier 5E7h, 8-bit CRC tester) assures absolute traceability because no two parts are alike
• EPROM partitioned into 256-bit pages for randomly accessing packetized data records

• Open drain PIO pins are controlled and their logic level can be determined over 1-Wire bus for closed-loop control
• Replaces and is fully compatible with DS2407 but no user-programmable power-on settings and no Hidden Mode
• PIO channel A sink capability of 50mA at 0.4V with soft turn-on; channel B 8mA at 0.4V

• Open-drain PIO pin is controlled by matching 64-bit, laser-engraved registration number associated with each device
• Logic level of open drain output can be determined over 1-Wire® bus for closed-loop control
• PIO pin sink capability is greater than 4mA at 0.4V

• Easily Add Traceability and Relevant Information to Any Individual System
• Minimalist 1-Wire Interface Lowers Cost and Interface Complexity
• Wide Voltage and Temperature Operating Ranges Provide Robust System Performance

• 65,536 bits of read/write nonvolatile memory
• Overdrive mode boosts communication speed to 142 kbits per second
• 256-bit scratchpad ensures integrity of data transfer

• 16384 bits Electrically Programmable Read Only Memory (EPROM) communicates with the economy of one signal plus ground
• EPROM partitioned into sixty-four 256-bit pages for randomly accessing packetized data records
• Each memory page can be permanently write-protected to prevent tampering

• 256-bit Electrically Erasable Programmable Read Only Memory (EEPROM) communicates with the economy of one signal plus ground
• EEPROM organized as one 256-bit page
• 64-bit one-time programmable application register is automatically write-protected after programming

• Can Be Read in Less Than 5ms
• Operating Range: 2.8V to 6.0V, -40°C to +85°C
Common iButton Features
• Unique Factory-Lasered 64-Bit Registration Number Ensures Error-Free Device Selection and Absolute Traceability Because No Two Parts are Alike
• Built-In Multidrop Controller for 1-Wire Net
• Digital Identification by Momentary Contact

• Digital Thermometer Measures Temperatures from -55°C to +100°C in Typically 0.2s
• Zero Standby Power
• 0.5°C Resolution, Digital Temperature Reading is Two's Complement of °C Value

• 16384 bits of read/write nonvolatile memory
• 256-bit scratchpad ensures integrity of data transfer
• Overdrive mode boosts communication to 142kbps

• Real-time clock (RTC) with fully compatible 1-Wire® MicroLAN interface
• Uses the same binary time/date representation as the DS2404 but with 1 second resolution
• Clock accuracy ±2 minutes per month at 25°C

• 4096 bits of Read/Write Nonvolatile Memory (DS1993)
• 1024 bits of Read/Write Nonvolatile Memory (DS1992)
• 256-bit Scratchpad Ensures Integrity of Data Transfer

• 4096 bits of Read/Write Nonvolatile Memory (DS1993)
• 1024 bits of Read/Write Nonvolatile Memory (DS1992)
• 256-bit Scratchpad Ensures Integrity of Data Transfer