Maxim is committed to providing high-quality high-reliability surface-mount products. Nearly every product is offered in a surface-mount package. Surface-mount products are tested through the same production flow as dual-in-line (DIP) plastic devices and are tested to the same stringent electrical and visual AQL levels. Product qualification and reliability monitoring programs for DIP and surface-mount products are nearly identical. Surface-mount products are additionally subjected to preconditioning prior to many reliability tests. Refer to our product reliability report for details.
Maxim surface-mount packages are shipped in antistatic plastic rails. For customers using automatic placement systems, parts also come mounted in pockets on embossed tape. The tape is wound and shipped on reels. The table and diagram on this page indicate the tape sizes used for various package types and the basic orientation convention used. Further tape-and-reel specifications can be found in the Electronic Industries Association (EIA) Standard 481.
Tape and Reel Packaging Information
Tape and reel packaging table (PDF)
Moisture Sensitivity Levels for Maxim SMD Packages (PDF)
Moisture Sensitivity Levels for Dallas Semiconductor SMD Packages (PDF)
Tape and Reel Packaging Diagrams
Figure 1. General tape and reel orientation.
Figure 1a. Quadrant designation. Use pin 1 mark to determine the correct orientation of unit in reel.
Figure 2. SOIC/SSOP/TSSOP/MSOP/QSOP/TSOC.
Figure 3a. SOT-23 Maxim part numbers (COMETS) – MAX prefix.
Figure 3b. SOT-23 Dallas part numbers (MAXCIM) – DS prefix.
Figure 4. PLCC/TQFP/LQFP/MQFP/BGA.
Figure 5. SC70.
Figure 6. T/QFN/LGA/TDFN.
Figure 7. Other TQFN/TDFN/UDFN/ODFN/BGA.
Figure 8. SFN dead bug.
Figure 9. Mechanical polarization SOT223 device.
Figure 10. WLP/UCSP™/UCSP-R.
Figure 11a. TO-92 rounded side of transistor and adhesive tape visible (style A).
Figure 11b. Flat side of transistor and carrier strip visible (style B).
Figure 11c. Flat side of transistor and adhesive tape visible (style E).
Figure 11d. Rounded side of transistor and carrier strip visible (style F).
Figure 12. Rounded side transistor and adhesive tape visible (style straight leads).