IC package technical information is a crucial component of any circuit design, impacting not only schematic details, PCB size and layout but also environmental and reliability considerations. Our comprehensive portfolio of IC package technical data provides information on package types, package outlines, IC package land patterns, lead-free and RoHS compliance, environmental data and IC package materials data. Many of our IC’s are available in Wafer-Level Packaging (WLP). The WLP package uses individual solder balls to connect the integrated circuit to a printed-circuit board (PCB), with the IC mounted face-down. This technology differs from other ball-grid array, leaded, and laminate-based chip-scale packages (CSP) because there are no bond wires or interposer connections. The principal advantage is that IC-to-PCB board inductance is minimized. Secondary benefits include reduction in package size and manufacturing cycle time and enhanced thermal conduction characteristics. We provide a number of application notes that discuss the main considerations and guidelines for mounting integrated circuit packages on a PCB.
|Application Note||5963||Quad Flat Package No Leads (QFN) Design, Fabrication & Assembly|
|Application Note||4132||Attachment Methods for the Electro-Mechanical 1-Wire Contact Package|
|Tutorial||4083||Thermal Characterization of IC Packages|
|Application Note||4002||Understanding Flip-Chip and Chip-Scale Package Technologies and Their Applications|
|Application Note||3930||Package Thermal Resistance Values (Theta JA, Theta JC) for Temperature Sensors and 1-Wire Devices|
|Application Note||3924||Thermal Considerations for a UCSP Package|
|Application Note||1891||Wafer-Level Packaging (WLP) and its Applications|