Ask Michael: Swipe Right for the Isolated Gate Driver That’s a Perfect Match for GaN/SiC Switches
December 17, 2019
| By: Michael Jackson
Principal Writer, Maxim Integrated
I've heard that gallium nitride (GaN) and silicon carbide (SiC) could replace MOSFET and IGBT power switches in the near future. The fact that they are smaller and faster sounds great, but as always, I suspect there's no such thing as a free lunch. Are there any pitfalls that I need to be aware of before I start looking at using GaN and SiC in my designs?
You've heard right. As energy efficiency becomes increasingly important, GaN and SiC transistors, being both smaller and faster than current high-power switch technologies, look perfectly poised to step into the limelight. However, it's not quite a straight-swap. Choosing to use them will have implications for your choice of gate driver circuit, as I'll now explain with a couple of examples:
Figure 1 shows a circuit where a low-voltage microcontroller is galvanically isolated (for safety reasons) from the high-voltage domain that includes the output switches and their gate driver. Faster switching speeds mean faster switching transients. For example, GaN power systems typically switch in 5ns (an order of magnitude faster than conventional MOSFET systems). Assuming a typical 600V high-voltage rail, this results in a (600V/5ns) = 120kV/μs switching transient.
Figure 1. Typical isolated power converter circuit.
Fast noise transients can corrupt data transmission across the isolation barrier or, worse, cause a glitch that could trigger both power FETs to turn ON at the same time, triggering a hazardous electrical short circuit. To prevent this situation from arising, fast switching technologies need a gate-driver common-mode transient immunity (CMTI) of at least 120kV/μs for designs using a typical 600V high-voltage rail. CMTI is defined as the maximum tolerable rate of rise or fall of the common-mode voltage applied between two isolated circuits. The unit is normally in kV/μs. High CMTI means that signal level on either side of the isolation barrier is preserved (to within datasheet limits) when the isolation barrier is struck with a high-voltage common-mode signal.
Propagation Delay Matching
The second thing you need to watch out for relates to the on/off timing of the switches. In the circuit shown in Figure 2, under no circumstances should both switches be "on" at the same time, as this would lead to a short-circuit type (usually referred to as shoot-through) condition.
Figure 2. Half-bridge push-pull circuit.
To prevent this from happening, the design must allow for a small amount of "dead time" where both switches are "off." However, GaN switches continue to conduct some current, even when reverse biased. This reduces efficiency as not all power is transferred to the load during this time. Therefore, there is a trade-off to be made between leaving a sufficiently safe "dead time" and the reduced efficiency that this causes. Arriving at an optimal solution requires an understanding of the variability in the propagation delay between individual gate driver parts, referred to as part-to-part (or channel-to-channel for parts with multiple channels) propagation delay matching, or skew. When designing for this type of circuit, a gate driver with the lowest possible propagation delay skew is the best choice as it helps minimize the amount of dead time, while ensuring that a "shoot through" condition can never occur.
The Best of Both Worlds
You'll be glad to know that there is a family of isolated gate driver ICs that solves both problems. Figure 3 shows a functional diagram for the MAX22700D/MAX22702D. These come with the highest available level of CMTI of 300kV/µs. Propagation delay skew is only 2ns (maximum) at room temperature and 5ns (maximum) over the -40°C to +125°C operating temperature range, helping to minimize dead time in your designs and, hence, increase efficiency.
Figure 3. MAX22700D/MAX22702D high CMTI isolated gate driver.
Other benefits of these parts include a precision undervoltage lockout (UVLO) which ensures that multiple parts driving switches in parallel operate at the same starting voltage. This is important when setting the VGS for SiC transistors. There are several variants with output options for the gate driver common pin: GNDB (MAX22700), Miller clamp (MAX22701), and adjustable UVLO (MAX22702). In addition, differential (D versions) or single-ended (E versions) input versions are available. The isolation barrier has a withstand voltage rating of 3kVRMS for 60s to provide robust performance. These ICs can drive SiC or GaN FETs with different output gate drive circuitry and B-side supply voltages.
So, Mary, I hope that you have a better idea of what to watch for when you start designing with GaN/SiC switches and that I've shown you a part that's been designed precisely for engineers in your position.
All the best,