How PA Linearization Solves Key Challenge for Remote PHY Fiber Nodes

October 13, 2017

Christine Young By: Christine Young
Blogger, Maxim Integrated 


Designing cable remote PHY fiber nodes? Check out Maxim’s new power amplifier (PA) linearization solution using open-loop digital predistortion (DPD). With this open-loop DPD solution and the MAX5850 14-bit, 3.072Gsps RF DAC, you’ll be able to reduce PA power consumption by 28% without adding additional components and complexity to your designs.

The DPD solution includes state-of-the-art technology from Qorvo, a leading provider of innovative RF solutions. Qorvo’s RFPD3580 GaAs/GaN hybrid power doubler offers extremely high output power and optimum distortion performance. Maxim has partnered with Qorvo to characterize the RFPD3580 and optimize the DPD solution for this PA.

Live Demo at SCTE Cable-Tec Expo

Maxim and Qorvo will have a live demo of their DPD/DAC/PA linearization solution at the SCTE Cable-Tec Expo in Denver, from October 18 to 20. Reserve a private meeting with Maxim at Booth 801 at the show, and our experts will show you how the solution works. You can also learn more by sending an email with your questions to analog@maximintegrated.com.

Rajeev Krishnamoorthy, Maxim's GM for timing and datacom products, explained of the solution, "Maxim and Qorvo working together closely have solved the complex cable PA linearization system-level problem. Maxim's DPD solution not only significantly reduces PA power dissipation, it also reduces complexity and eases implementation. A single set of DPD coefficients can be used to linearize PAs over temperature across multiple RF boards for a given design. PA matching or binning isn’t required to implement this open-loop DPD solution."

Maxim's Open-Loop DPD/DAC/PA Linearization Solution for Remote PHY Fiber Nodes

In addition to lowering power, you can also use this open-loop DPD solution to reduce complexity and cost in your designs. With the DPD solution, the bias of the Qorvo RFPD3580 (18W at full bias, 34V) can be reduced 28% (530mA down to 380mA) or 5.1W per PA while maintaining 73.8dBmV total composite power at the node output. Since the solution is open-loop and doesn't require additional circuitry, it can be integrated into existing designs with minimal disruption and has a low implementation cost. Competing closed-loop solutions require an observation receiver path (RF sampling ADC), additional FPGA resources to capture and process the data from the feedback path, and an RF switch to sample the outputs of multiple PAs—all of which consume board space and add cost, power, and complexity.