Higher Throughput at Lower Cost for Semiconductor Testing

June 11, 2019

Robert Gee  By: Robert Gee
 Executive Business Manager, Core Product Group, Maxim Integrated 

In the semiconductor testing world, managing cost remains one of the toughest challenges, since automated test equipment (ATE) represents a major capital expenditure. One way to reduce the cost per wafer—and, therefore, gain a competitive advantage? Increase throughput.

Semiconductor manufacturers evaluating new ATE systems for their fabs demand higher densities (i.e., more channels) with each generation—but in the same form factor to maximize the use of their existing factory floor space. With more channels, they can test more complicated products or higher volumes of the same product.

In this climate, it’s not uncommon for ATE designers to strive to boost the number of channels in each generation. Increasing the testing capability means that the main board—a driver board with a lot of pin driver electronics—will require a substantial amount of power to operate. Of course, from a long-term performance and reliability standpoint, it’s important to keep the equipment temperature down. This means that the underlying technology should be highly efficient, fast performing, and small.

Silicon wafer probe testingIncreasing throughput is one of the best ways to reduce testing cost per wafer.

Dual-Channel Pin Electronics for ATE Systems
Designers creating new ATE systems can increase the number of channels while maintaining the same form factor by placing the ICs on a board closer together. This would create more power dissipation, which could be addressed with either heat sinks for air cooling or with liquid cooling. Liquid cooling, however, is a complex solution that requires a highly specialized skill set.

Alternatively, designers can take a closer look at the pin electronics inside the equipment. An IC offering a higher level of integration will provide the functions needed without adding to the bill of materials (BOM) or increasing the size of the design with discrete components. The process geometry for the IC also bears consideration. An IC under consideration may support a large number of channels, but was it manufactured with a process that results in the efficiency and size needed for the design?

Maxim has a custom-designed wafer process that’s optimized for ATE architectures, and the MAX9979 dual-channel 1.1Gbps pin electronics was manufactured on this process. In a single IC, ideal for memory and SoC tester applications, the MAX9979 provides:

  • Driver/comparator/active load (DCL)
  • Per-channel parametric measurement unit (PMU)
  • Built-in, 16-bit, level-setting digital-to-analog converters (DACs)

Each channel includes a four-level pin driver, window comparator, differential comparator, dynamic clamps, a versatile PMU, an active load, a high-voltage programmable level, and 14 independent level-setting DACs. The device was designed on a process that has gold interconnects—not typically a standard feature, but one that supports higher power density. Its bipolar transistors were designed to provide symmetrical switching; as such, the rise and fall times are very well matched, so when a signal is sent to the device being tested, the quality of that signal is about as symmetrical as possible in a system.

Another performance advantage comes from the IC’s cable droop compensation feature. This capability allows the designer to fine-tune every channel to optimize the waveform to the device under test (DUT). With multiple channels on a board, not all of them will have the same length of tracing or coaxial cable to the DUT. Cable droop compensation uses a double time-constant to change the waveform so that when the waveform gets to the DUT, it will be as symmetrical as possible. This ability to calibrate the driving of signals to the DUT and the same signals on the return path of each individual channel yields clearer signal quality. Without an ability to correct or adjust the waveform, the choice of the coaxial cables used in the ATE design becomes more critical. Each test head can use hundreds of these cables. A lower quality, and perhaps less expensive, cable can cause signal distortion. The ability to correct the waveform mitigates this distortion. Without this capability, the main way to achieve high-quality signals would be to use higher quality, and more expensive, coaxial cables.

To evaluate the MAX9979 for your next design, check out the MAX9979 evaluation kit. A fully assembled and tested PCB, the kit includes SMA connections for the high-speed digital I/Os, the MAX9979 pin driver outputs, and a user-configurable Windows GUI, providing an easy to way to fully evaluate the IC.

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