Applying Peak Current Mode Control for High Performance in Switching Regulators

January 30, 2018

John Woodward By: John Woodward
Executive Business Manager, Industrial Power, Maxim Integrated 


There are a variety of different control schemes used to achieve output voltage regulation. Current mode control, in its simplest form where peak switch current is monitored, has some really nice benefits. It's a popular way to achieve high performance in switching regulators. There are some considerations in a practical design that need attention, but these are easily addressed, as I’ll discuss in this post.

Benefits of Peak Current Mode Control

Figure 1 shows the basic implementation of peak current mode control in a buck converter. There are two control loops in operation: a fast inner one which compares a control signal Ve with an analog of switch current Vcs to set pulse width, and a slower outer loop which compares output voltage with a reference to generate the control signal for the inner loop. The effect is to form a controlled current source for the output capacitor and load, with the inductor 'disappearing' from the transfer function while regulating output voltage. The double pole associated with the output LC network becomes a single pole, which is much easier to stabilize, especially with ceramic output capacitors with their inherent low ESR and high frequency zero. This has the benefit of simplifying loop compensation and enabling wider bandwidth and faster load transient response.

Peak current mode control scheme

Figure 1. Peak current mode control scheme

With current mode control, it's easy to protect the switch from over-current, as the current sense signal can be compared with a reference to give a fast shutdown if it exceeds a set value. There is also a natural fast 'feed-forward' effect where changes in input voltage are immediately reflected in switch current ramp rate, directly affecting the switch-off point without having to wait for an error in the output voltage to propagate around the slow outer loop before correction.

There are a couple of things to look out for, though, when designing with peak current mode control: noise pickup and sub-harmonic instability.

Noisy Signals

There's a conflict between keeping dissipation in current sensing elements low and having sufficient resultant voltage to avoid noise problems. In typical schemes, the voltage from the maximum sensed current might be around 1V, but at light loads the value is proportionally less. Spikes on the current signal edges due to di/dt through circuit inductances, charge and discharge of parasitic capacitances, and diode reverse recovery transients are inevitable. These can cause premature shutdown of the regulator and chaotic operation as they become proportionally more of the signal at light loads. Careful board layout certainly helps, as does appropriate snubbing, but usually this is not enough under all conditions. A simple RC filter on the sense signal attenuates spikes but adds delay, makes current-limiting less accurate, and leads to loss of control at low loads and low duty cycles. A current sense transformer is a way to get useable voltage levels with little dissipation, but it can be expensive and unwieldy compared with resistive sensing. Reset of the transformer at high duty cycles can also be a problem.

An effective solution is resistive sensing at low voltage levels, with leading-edge blanking where the control chip ignores the current sense signal for a fixed period, typically 50ns at the beginning of each cycle. As integration of MOSFETs and ultimately magnetics into chips progresses at companies such as Maxim, the problem recedes; the switching current loops get smaller and more predictable, and the IC manufacturer is able to internally compensate for the transients.

More exotic techniques can use the resistance of the output inductor itself to sense current. However, circuitry is needed to subtract the normal switching waveform from the resistive volt-drop and to compensate for the significant variation in resistance of the copper winding with temperature.

Sub-Harmonic Instability

Sub-harmonic instability stems from controlling peak inductor current instead of the ideal of controlling average current. If the duty cycle of a buck converter is less than 50%, a small disturbance in input voltage causes a small change in peak-to-peak ripple current. A negative disturbance in input voltage causes a decrease in peak-to-peak ripple current. As the off-time is greater than the on-time (<50% DC), the current has time to ramp down to a new steady-state value equal to its starting cycle current. At duty cycles higher than 50%, the off-time is shorter than the on-time and the inductor current ramping down doesn’t get back to the starting value, so the next cycle starts with a higher ripple current, making the average current temporarily higher. The load current is constant so the increase can only flow into the output capacitor, raising its voltage slightly. The control loop corrects the resultant output voltage error over several cycles, but in the meantime, the pulse width 'jitters' at typically half the switching frequency. See Figure 2.

Figure 2. Sub-harmonic instability with D>0.5

The solution for this is to artificially add some slope to the on-time sensed current waveform, which can be easily derived from the IC clock signal. The extra slope can alternatively be subtracted from the error voltage. The technique is shown in Figure 3.

Adding slope compensation

It can be shown that if a slope is added at the comparator input equal to 50% of the equivalent signal from the inductor downslope, the peak current detection point adjusts to make the average inductor current constant with duty cycle perturbations. This ensures that disturbances die out in one switching cycle and stability is maintained. In practice, more slope is often added up to 100% of the current sense signal to ensure stability up to high duty cycles. If excess slope is added, the converter increasingly loses the benefits of current mode control and performs more as if it is in voltage mode.

The downslope di/dt of the inductor waveform is fixed for a given output voltage Vout and inductance L.

Downslope Equation

This does mean that in simple circuits, slope compensation cannot always be optimum for a variable output voltage, although it is possible to have variable compensation with more complexity – a good candidate for digital control functionality.

In control ICs with high levels of integration such as those in the Maxim portfolio, the complexity of slope compensation is handled internally with current sensing and level shifting, making life that much easier for the designer. To learn more about various aspects of power supply design, including switching regulators, watch the Power System Design Seminar, a video series hosted by Bob Mammano, the father of the first switch-mode power supply.