DS1685/87 and DS17X85/87 Accessing Extended User RAM
Abstract: This application note describes how to use the extended RAM that is available in some multiplexed-bus real-time clocks (RTCs).
The DS1685/87 and DS17x85/87 include an additional block of extended user RAM. The memory capacity of each device varies as follows; the DS1685/87 provides 1,024 bits organized in a 128 x 8 block, and the DS17x85/87 provides 16,384, 32,768 or 65,536, bits organized in 2kbits x 8, 4kbits x 8, or 8kbits x 8, blocks respectively.
Figure 1 illustrates how the register blocks have been partitioned into two separate banks, bank 0 and bank 1. A bank select bit, DV0 located in control register 0Ah (bit 4), is used to select which register bank to make accessible. When DV0 is written to a logic 0, bank 0 is selected and an additional 64 bytes of user RAM can be accessed. However, when DV0 is written to a logic 1, bank 1 is selected and the additional features, including the extended user RAM, can be accessed. The real time clock (RTC), control registers, and 50 bytes of user RAM are accessible from either bank, independent of the DV0 bit.
Figure 1. Register block partition.
Software Communication Ports
The extended user RAM communication ports reside in the bank 1 register block. The extended user RAM address ports are located in registers 50h and 51h, while the extended user RAM data port is located in register 53h. Register 50h contains the LSB address and register 51h contains the MSB address. The DS1685/87 requires only 7 bits to address the extended RAM and therefore does not require the MSB address register 51h. These three bank 1 registers provide the software interface necessary to access the extended user RAM. The steps involved to read from and write to the extended RAM are listed below:
An automatic address increment feature, available with the DS17x85/87, simplifies the software required to access the extended user RAM. This feature can be enabled or disabled with a single bit, located in extended control register 4Ah, bit 5. This feature simplifies the software required to access consecutive RAM address locations.
- Write the DV0 bit to a logic 1
- Write the LSB address to register 50h
- Write the MSB address (if required) to register 51h
- Read from or write to the data register, 53h
Protocol for PC Applications
The processor I/O ports used to access CMOS RAM are 70h and 71h. Port 70h is the CMOS RAM address register and port 71h is the CMOS RAM data register. The flow chart shown in Figure 2 illustrates the software protocol for PC applications.
Figure 2. PC software protocol flow chart.
The extended user RAM software access method provides the user with the greatest flexibility when determining which RAM density is needed, without any hardware modifications, for the DS1685/87 and DS17x85/87 (2kbits, 4kbits, and 8kbits) devices.
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|© May 31, 2001, Maxim Integrated Products, Inc.
APP 77: May 31, 2001
APPLICATION NOTE 77,