-- *********************************************************************** -- BSDL file for design DS3144_CSBGA_144 -- Created by Synopsys Version 2000.11 (Nov 27, 2000) -- Designer: -- Company: Dallas Semiconductor -- Date: Sat Feb 2 17:07:06 2002 -- *********************************************************************** entity DS3144_CSBGA_144 is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "CSBGA_144"); -- This section declares all the ports in the design. port ( ADDR0 : in bit; ADDR1 : in bit; ADDR2 : in bit; ADDR3 : in bit; ADDR4 : in bit; ADDR5 : in bit; ADDR6 : in bit; ADDR7 : in bit; ADDR8 : in bit; ADDR9 : in bit; ALE : in bit; CS_N : in bit; HIZ_N : in bit; JTCLK : in bit; JTDI : in bit; JTMS : in bit; JTRST_N : in bit; MOT : in bit; RCLK1 : in bit; RCLK2 : in bit; RCLK3 : in bit; RCLK4 : in bit; RD_N : in bit; RECU : in bit; RNEG1 : in bit; RNEG2 : in bit; RNEG3 : in bit; RNEG4 : in bit; RPOS1 : in bit; RPOS2 : in bit; RPOS3 : in bit; RPOS4 : in bit; RST_N : in bit; SCLK : in bit; TDAT1 : in bit; TDAT2 : in bit; TDAT3 : in bit; TDAT4 : in bit; TEST_N : in bit; TICLK1 : in bit; TICLK2 : in bit; TICLK3 : in bit; TICLK4 : in bit; TMEI : in bit; TOH1 : in bit; TOH2 : in bit; TOH3 : in bit; TOH4 : in bit; TOHEN1 : in bit; TOHEN2 : in bit; TOHEN3 : in bit; TOHEN4 : in bit; WR_N : in bit; DATA0 : inout bit; DATA1 : inout bit; DATA2 : inout bit; DATA3 : inout bit; DATA4 : inout bit; DATA5 : inout bit; DATA6 : inout bit; DATA7 : inout bit; INT_N : inout bit; TSOF1 : inout bit; TSOF2 : inout bit; TSOF3 : inout bit; TSOF4 : inout bit; JTDO : out bit; RDAT1 : out bit; RDAT2 : out bit; RDAT3 : out bit; RDAT4 : out bit; RDEN1 : out bit; RDEN2 : out bit; RDEN3 : out bit; RDEN4 : out bit; RLOS1 : out bit; RLOS2 : out bit; RLOS3 : out bit; RLOS4 : out bit; ROCLK1 : out bit; ROCLK2 : out bit; ROCLK3 : out bit; ROCLK4 : out bit; ROOF1 : out bit; ROOF2 : out bit; ROOF3 : out bit; ROOF4 : out bit; RSOF1 : out bit; RSOF2 : out bit; RSOF3 : out bit; RSOF4 : out bit; TCLK1 : out bit; TCLK2 : out bit; TCLK3 : out bit; TCLK4 : out bit; TDEN1 : out bit; TDEN2 : out bit; TDEN3 : out bit; TDEN4 : out bit; TNEG1 : out bit; TNEG2 : out bit; TNEG3 : out bit; TNEG4 : out bit; TPOS1 : out bit; TPOS2 : out bit; TPOS3 : out bit; TPOS4 : out bit; VDD : linkage bit_vector (1 to 12); VSS : linkage bit_vector (1 to 12) ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of DS3144_CSBGA_144: entity is "STD_1149_1_1993"; attribute PIN_MAP of DS3144_CSBGA_144: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information -- is extracted from the port-to-pin map file that was read in using -- the "read_pin_map" command. constant CSBGA_144: PIN_MAP_STRING := "ADDR0 : E3," & "ADDR1 : G3," & "ADDR2 : J3," & "ADDR3 : K5," & "ADDR4 : K7," & "ADDR5 : K9," & "ADDR6 : H10," & "ADDR7 : F10," & "ADDR8 : E10," & "ADDR9 : D10," & "ALE : C7," & "CS_N : C6," & "HIZ_N : J8," & "JTCLK : E4," & "JTDI : H4," & "JTMS : D5," & "JTRST_N : D4," & "MOT : C8," & "RCLK1 : C1," & "RCLK2 : K12," & "RCLK3 : A10," & "RCLK4 : M3," & "RD_N : C4," & "RECU : J9," & "RNEG1 : A1," & "RNEG2 : M12," & "RNEG3 : A12," & "RNEG4 : M1," & "RPOS1 : B1," & "RPOS2 : L12," & "RPOS3 : A11," & "RPOS4 : M2," & "RST_N : D8," & "SCLK : D9," & "TDAT1 : A6," & "TDAT2 : M7," & "TDAT3 : F12," & "TDAT4 : G1," & "TEST_N : J5," & "TICLK1 : A7," & "TICLK2 : M6," & "TICLK3 : G12," & "TICLK4 : F1," & "TMEI : H9," & "TOH1 : B7," & "TOH2 : L6," & "TOH3 : G11," & "TOH4 : F2," & "TOHEN1 : B8," & "TOHEN2 : L5," & "TOHEN3 : H11," & "TOHEN4 : E2," & "WR_N : C5," & "DATA0 : D3," & "DATA1 : F3," & "DATA2 : H3," & "DATA3 : K4," & "DATA4 : K6," & "DATA5 : K8," & "DATA6 : J10," & "DATA7 : G10," & "INT_N : C9," & "TSOF1 : B5," & "TSOF2 : L8," & "TSOF3 : E11," & "TSOF4 : H2," & "JTDO : J4," & "RDAT1 : D1," & "RDAT2 : J12," & "RDAT3 : A9," & "RDAT4 : M4," & "RDEN1 : D2," & "RDEN2 : J11," & "RDEN3 : B9," & "RDEN4 : L4," & "RLOS1 : A2," & "RLOS2 : M11," & "RLOS3 : B12," & "RLOS4 : L1," & "ROCLK1 : E1," & "ROCLK2 : H12," & "ROCLK3 : A8," & "ROCLK4 : M5," & "ROOF1 : B2," & "ROOF2 : L11," & "ROOF3 : B11," & "ROOF4 : L2," & "RSOF1 : C2," & "RSOF2 : K11," & "RSOF3 : B10," & "RSOF4 : L3," & "TCLK1 : A5," & "TCLK2 : M8," & "TCLK3 : E12," & "TCLK4 : H1," & "TDEN1 : B6," & "TDEN2 : L7," & "TDEN3 : F11," & "TDEN4 : G2," & "TNEG1 : A4," & "TNEG2 : M9," & "TNEG3 : D12," & "TNEG4 : J1," & "TPOS1 : B4," & "TPOS2 : L9," & "TPOS3 : D11," & "TPOS4 : J2," & "VDD : (D6, E5, E6, F4, F5, F6, G7, G8, G9, H7, H8, J7)," & "VSS : (D7, E7, E8, F7, F8, F9, G4, G5, G6, H5, H6, J6)"; -- This section specifies the TAP ports. -- For the TAP TCK port, the parameters in the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of JTCLK : signal is (10.0e6, BOTH); attribute TAP_SCAN_IN of JTDI : signal is true; attribute TAP_SCAN_MODE of JTMS : signal is true; attribute TAP_SCAN_OUT of JTDO : signal is true; attribute TAP_SCAN_RESET of JTRST_N: signal is true; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of DS3144_CSBGA_144: entity is 3; -- Specifies the boundary-scan instructions implemented in the -- design and their opcodes. attribute INSTRUCTION_OPCODE of DS3144_CSBGA_144: entity is "BYPASS (111)," & "EXTEST (000)," & "SAMPLE (010)," & "CLAMP (011)," & "HIGHZ (100)," & "USER1 (101)," & "USER2 (110)," & "IDCODE (001)"; -- Specifies the bit pattern that is loaded into the instruction -- register when the TAP controller passes through the Capture-IR -- state. The standard mandates that the two LSBs must be "01". -- The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of DS3144_CSBGA_144: entity is "001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID -- register during the IDCODE instruction when the TAP controller -- passes through the Capture-DR state. attribute IDCODE_REGISTER of DS3144_CSBGA_144: entity is "0001" & -- 4-bit version number "0000000000010100" & -- 16-bit part number "00010100001" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 -- This section specifies the test data register placed between TDI -- and TDO for each implemented instruction. attribute REGISTER_ACCESS of DS3144_CSBGA_144: entity is "BYPASS (BYPASS, CLAMP, HIGHZ, USER1, USER2)," & "BOUNDARY (EXTEST, SAMPLE)," & "DEVICE_ID (IDCODE)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of DS3144_CSBGA_144: entity is 125; -- The following list specifies the characteristics of each cell -- in the boundary scan register from TDI to TDO. -- The following is a description of the label fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not -- have a port name. -- function: Is the function of the cell as defined by the -- standard. Is one of input, output2, output3, -- bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be -- loaded with for safe operation when the software -- might otherwise choose a random value. -- ccell : The control cell number. Specifies the control -- cell that drives the output enable for this port. -- disval : Specifies the value that is loaded into the -- control cell to disable the output enable for -- the corresponding port. -- rslt : Resulting state. Shows the state of the driver -- when it is disabled. attribute BOUNDARY_REGISTER of DS3144_CSBGA_144: entity is -- -- num cell port function safe [ccell disval rslt] -- "124 (BC_4, INT_N, observe_only, X), " & "123 (BC_0, *, internal, X), " & "122 (BC_2, INT_N, output2, 1, 122, 1, WEAK1)," & "121 (BC_4, SCLK, observe_only, X), " & "120 (BC_4, MOT, observe_only, X), " & "119 (BC_4, RST_N, observe_only, X), " & "118 (BC_4, ALE, observe_only, X), " & "117 (BC_4, CS_N, observe_only, X), " & "116 (BC_4, WR_N, observe_only, X), " & "115 (BC_4, RD_N, observe_only, X), " & "114 (BC_4, TOHEN1, observe_only, X), " & "113 (BC_4, TOH1, observe_only, X), " & "112 (BC_4, TICLK1, observe_only, X), " & "111 (BC_4, TDAT1, observe_only, X), " & "110 (BC_2, TDEN1, output3, X, 109, 1, Z), " & "109 (BC_2, *, controlr, 1), " & "108 (BC_2, TCLK1, output3, X, 109, 1, Z), " & "107 (BC_4, TSOF1, observe_only, X), " & "106 (BC_2, TSOF1, output3, X, 105, 1, Z), " & "105 (BC_2, *, controlr, 1), " & "104 (BC_2, TNEG1, output3, X, 109, 1, Z), " & "103 (BC_2, TPOS1, output3, X, 109, 1, Z), " & "102 (BC_2, RLOS1, output3, X, 109, 1, Z), " & "101 (BC_4, RNEG1, observe_only, X), " & "100 (BC_4, RPOS1, observe_only, X), " & "99 (BC_2, ROOF1, output3, X, 109, 1, Z), " & "98 (BC_4, RCLK1, observe_only, X), " & "97 (BC_2, RSOF1, output3, X, 109, 1, Z), " & "96 (BC_2, RDAT1, output3, X, 109, 1, Z), " & "95 (BC_2, RDEN1, output3, X, 109, 1, Z), " & "94 (BC_2, ROCLK1, output3, X, 109, 1, Z), " & "93 (BC_4, DATA0, observe_only, X), " & "92 (BC_2, DATA0, output3, X, 91, 1, Z), " & "91 (BC_2, *, controlr, 1), " & "90 (BC_4, ADDR0, observe_only, X), " & "89 (BC_4, DATA1, observe_only, X), " & "88 (BC_2, DATA1, output3, X, 91, 1, Z), " & "87 (BC_4, ADDR1, observe_only, X), " & "86 (BC_4, DATA2, observe_only, X), " & "85 (BC_2, DATA2, output3, X, 91, 1, Z), " & "84 (BC_4, ADDR2, observe_only, X), " & "83 (BC_4, TOHEN4, observe_only, X), " & "82 (BC_4, TOH4, observe_only, X), " & "81 (BC_4, TICLK4, observe_only, X), " & "80 (BC_4, TDAT4, observe_only, X), " & "79 (BC_2, TDEN4, output3, X, 78, 1, Z), " & "78 (BC_2, *, controlr, 1), " & "77 (BC_2, TCLK4, output3, X, 78, 1, Z), " & "76 (BC_4, TSOF4, observe_only, X), " & "75 (BC_2, TSOF4, output3, X, 74, 1, Z), " & "74 (BC_2, *, controlr, 1), " & "73 (BC_2, TNEG4, output3, X, 78, 1, Z), " & "72 (BC_2, TPOS4, output3, X, 78, 1, Z), " & "71 (BC_2, RLOS4, output3, X, 78, 1, Z), " & "70 (BC_4, RNEG4, observe_only, X), " & "69 (BC_4, RPOS4, observe_only, X), " & "68 (BC_2, ROOF4, output3, X, 78, 1, Z), " & "67 (BC_4, RCLK4, observe_only, X), " & "66 (BC_2, RSOF4, output3, X, 78, 1, Z), " & "65 (BC_2, RDAT4, output3, X, 78, 1, Z), " & "64 (BC_2, RDEN4, output3, X, 78, 1, Z), " & "63 (BC_2, ROCLK4, output3, X, 78, 1, Z), " & "62 (BC_4, DATA3, observe_only, X), " & "61 (BC_2, DATA3, output3, X, 91, 1, Z), " & "60 (BC_4, ADDR3, observe_only, X), " & "59 (BC_4, TEST_N, observe_only, X), " & "58 (BC_4, DATA4, observe_only, X), " & "57 (BC_2, DATA4, output3, X, 91, 1, Z), " & "56 (BC_4, ADDR4, observe_only, X), " & "55 (BC_4, DATA5, observe_only, X), " & "54 (BC_2, DATA5, output3, X, 91, 1, Z), " & "53 (BC_4, ADDR5, observe_only, X), " & "52 (BC_4, HIZ_N, observe_only, X), " & "51 (BC_4, TOHEN2, observe_only, X), " & "50 (BC_4, TOH2, observe_only, X), " & "49 (BC_4, TICLK2, observe_only, X), " & "48 (BC_4, TDAT2, observe_only, X), " & "47 (BC_2, TDEN2, output3, X, 46, 1, Z), " & "46 (BC_2, *, controlr, 1), " & "45 (BC_2, TCLK2, output3, X, 46, 1, Z), " & "44 (BC_4, TSOF2, observe_only, X), " & "43 (BC_2, TSOF2, output3, X, 42, 1, Z), " & "42 (BC_2, *, controlr, 1), " & "41 (BC_2, TNEG2, output3, X, 46, 1, Z), " & "40 (BC_2, TPOS2, output3, X, 46, 1, Z), " & "39 (BC_2, RLOS2, output3, X, 46, 1, Z), " & "38 (BC_4, RNEG2, observe_only, X), " & "37 (BC_4, RPOS2, observe_only, X), " & "36 (BC_2, ROOF2, output3, X, 46, 1, Z), " & "35 (BC_4, RCLK2, observe_only, X), " & "34 (BC_2, RSOF2, output3, X, 46, 1, Z), " & "33 (BC_2, RDAT2, output3, X, 46, 1, Z), " & "32 (BC_2, RDEN2, output3, X, 46, 1, Z), " & "31 (BC_2, ROCLK2, output3, X, 46, 1, Z), " & "30 (BC_4, DATA6, observe_only, X), " & "29 (BC_2, DATA6, output3, X, 91, 1, Z), " & "28 (BC_4, ADDR6, observe_only, X), " & "27 (BC_4, RECU, observe_only, X), " & "26 (BC_4, TMEI, observe_only, X), " & "25 (BC_4, DATA7, observe_only, X), " & "24 (BC_2, DATA7, output3, X, 91, 1, Z), " & "23 (BC_4, ADDR7, observe_only, X), " & "22 (BC_4, ADDR8, observe_only, X), " & "21 (BC_4, ADDR9, observe_only, X), " & "20 (BC_4, TOHEN3, observe_only, X), " & "19 (BC_4, TOH3, observe_only, X), " & "18 (BC_4, TICLK3, observe_only, X), " & "17 (BC_4, TDAT3, observe_only, X), " & "16 (BC_2, TDEN3, output3, X, 15, 1, Z), " & "15 (BC_2, *, controlr, 1), " & "14 (BC_2, TCLK3, output3, X, 15, 1, Z), " & "13 (BC_4, TSOF3, observe_only, X), " & "12 (BC_2, TSOF3, output3, X, 11, 1, Z), " & "11 (BC_2, *, controlr, 1), " & "10 (BC_2, TNEG3, output3, X, 15, 1, Z), " & "9 (BC_2, TPOS3, output3, X, 15, 1, Z), " & "8 (BC_2, RLOS3, output3, X, 15, 1, Z), " & "7 (BC_4, RNEG3, observe_only, X), " & "6 (BC_4, RPOS3, observe_only, X), " & "5 (BC_2, ROOF3, output3, X, 15, 1, Z), " & "4 (BC_4, RCLK3, observe_only, X), " & "3 (BC_2, RSOF3, output3, X, 15, 1, Z), " & "2 (BC_2, RDAT3, output3, X, 15, 1, Z), " & "1 (BC_2, RDEN3, output3, X, 15, 1, Z), " & "0 (BC_2, ROCLK3, output3, X, 15, 1, Z) "; end DS3144_CSBGA_144;