-- *********************************************************************** -- BSDL file for design ds31256_top -- Created by Synopsys Version 2000.11 (Nov 27, 2000) -- NOTE: The behaviour of the LINT, PINTA, and PSERR pins is incorrect -- in this BSDL file. It represents these pins as being capable -- of driving a 0 or 1, but they actually drive a 0 or Z. -- Currently, we do not have a solution for this problem. -- Designer: Dawn Murphy -- Company: Dallas Semiconductor / Maxim -- Date: Thu Oct 24 12:56:43 2002 -- *********************************************************************** entity ds31256_top is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "PBGA_256"); -- This section declares all the ports in the design. port ( JTCLK : in bit; JTDI : in bit; JTMS : in bit; JTRST : in bit; LCS : in bit; LHLDA : in bit; LIM : in bit; LMS : in bit; LRDY : in bit; PCLK : in bit; PGNT : in bit; PIDSEL : in bit; PRST : in bit; RC : in bit_vector (0 to 15); RD : in bit_vector (0 to 15); RS : in bit_vector (0 to 15); TC : in bit_vector (0 to 15); TS : in bit_vector (0 to 15); LINT : inout bit; LRD : inout bit; LWR : inout bit; PDEVSEL : inout bit; PFRAME : inout bit; PIRDY : inout bit; PPAR : inout bit; PPERR : inout bit; PSTOP : inout bit; PTRDY : inout bit; LA : inout bit_vector (0 to 19); LD : inout bit_vector (0 to 15); PAD : inout bit_vector (0 to 31); PCBE : inout bit_vector (0 to 3); JTDO : out bit; PINTA : buffer bit; PSERR : buffer bit; LBGACK : buffer bit; LBHE : buffer bit; LCLK : buffer bit; LHOLD : buffer bit; PREQ : buffer bit; PXAS : buffer bit; PXBLAST : buffer bit; PXDS : buffer bit; TD : buffer bit_vector (0 to 15); VDD : linkage bit_vector (1 to 16); VSS : linkage bit_vector (1 to 17) ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of ds31256_top: entity is "STD_1149_1_1993"; attribute PIN_MAP of ds31256_top: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information -- is extracted from the port-to-pin map file that was read in using -- the "read_pin_map" command. constant PBGA_256: PIN_MAP_STRING := "JTCLK : V19," & "JTDI : U18," & "JTMS : W20," & "JTRST : U19," & "LCS : K19," & "LHLDA : L18," & "LIM : M18," & "LMS : M19," & "LRDY : K18," & "PCLK : Y2," & "PGNT : W4," & "PIDSEL : Y6," & "PRST : W3," & "RC : (B1, D1, F2, H2, M1, P1, P4, V1, B17, B16, C14, D12, A10" & ", B8, B6, C5)," & "RD : (D2, E2, G3, J4, M3, R1, T2, U3, D16, C15, A14, B12, C10" & ", A7, D7, A3)," & "RS : (C2, E3, F1, H1, M2, P2, R3, T4, C17, A16, B14, C12, B10" & ", C8, A5, B4)," & "TC : (D3, E1, G2, J3, N1, P3, U1, V2, A18, D14, C13, A12, A9, " & "B7, C6, D5)," & "TS : (E4, F3, G1, J2, N2, R2, T3, W1, A17, B15, B13, B11, B9, " & "A6, B5, C4)," & "LINT : K20," & "LRD : H18," & "LWR : H19," & "PDEVSEL : Y11," & "PFRAME : W10," & "PIRDY : V10," & "PPAR : W12," & "PPERR : V11," & "PSTOP : W11," & "PTRDY : Y10," & "LA : (G20, G19, F20, G18, F19, E20, G17, F18, E19, D20, E18, " & "D19, C20, E17, D18, C19, B20, C18, B19, A20)," & "LD : (V20, U20, T18, T19, T20, R18, P17, R19, R20, P18, P19, " & "P20, N18, N19, N20, M17)," & "PAD : (V17, U16, Y18, W17, V16, Y17, W16, V15, W15, V14, Y15, " & "W14, Y14, V13, W13, Y13, V9, U9, Y8, W8, V8, Y7, W7, V7, U7, V6, Y5" & ", W5, V5, Y4, Y3, U5)," & "PCBE : (Y16, V12, Y9, W6)," & "JTDO : T17," & "PINTA : W18," & "PSERR : Y12," & "LBGACK : L20," & "LBHE : H20," & "LCLK : J20," & "LHOLD : L19," & "PREQ : V4," & "PXAS : V18," & "PXBLAST : Y20," & "PXDS : W19," & "TD : (C1, G4, H3, J1, N3, T1, U2, V3, C16, A15, A13, C11, C9, " & "C7, A4, B3)," & "VDD : (D6, D10, D11, D15, F4, F17, K4, K17, L4, L17, R4, R17, " & "U6, U10, U11, U15)," & "VSS : (A1, D4, D8, D9, D13, D17, H4, H17, J17, M4, N4, N17, U4" & ", U8, U12, U13, U17)"; -- This section specifies the TAP ports. -- For the TAP TCK port, the parameters in the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of JTCLK: signal is (10.0e6, BOTH); attribute TAP_SCAN_IN of JTDI : signal is true; attribute TAP_SCAN_MODE of JTMS : signal is true; attribute TAP_SCAN_OUT of JTDO : signal is true; attribute TAP_SCAN_RESET of JTRST: signal is true; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of ds31256_top: entity is 3; -- Specifies the boundary-scan instructions implemented in the -- design and their opcodes. attribute INSTRUCTION_OPCODE of ds31256_top: entity is "BYPASS (111)," & "EXTEST (000)," & "SAMPLE (010)," & "CLAMP (011)," & "HIGHZ (100)," & "IDCODE (001)"; -- Specifies the bit pattern that is loaded into the instruction -- register when the TAP controller passes through the Capture-IR -- state. The standard mandates that the two LSBs must be "01". -- The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of ds31256_top: entity is "001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID -- register during the IDCODE instruction when the TAP controller -- passes through the Capture-DR state. attribute IDCODE_REGISTER of ds31256_top: entity is "0000" & -- 4-bit version number "0000000000011010" & -- 16-bit part number "00010100001" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 -- This section specifies the test data register placed between TDI -- and TDO for each implemented instruction. attribute REGISTER_ACCESS of ds31256_top: entity is "BYPASS (BYPASS, CLAMP, HIGHZ)," & "BOUNDARY (EXTEST, SAMPLE)," & "DEVICE_ID (IDCODE)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of ds31256_top: entity is 214; -- The following list specifies the characteristics of each cell -- in the boundary scan register from TDI to TDO. -- The following is a description of the label fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not -- have a port name. -- function: Is the function of the cell as defined by the -- standard. Is one of input, output2, output3, -- bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be -- loaded with for safe operation when the software -- might otherwise choose a random value. -- ccell : The control cell number. Specifies the control -- cell that drives the output enable for this port. -- disval : Specifies the value that is loaded into the -- control cell to disable the output enable for -- the corresponding port. -- rslt : Resulting state. Shows the state of the driver -- when it is disabled. attribute BOUNDARY_REGISTER of ds31256_top: entity is -- -- num cell port function safe [ccell disval rslt] -- "213 (BC_1, *, controlr, 0), " & "212 (BC_0, LD(0), bidir, X, 213, 0, Z), " & "211 (BC_0, LD(1), bidir, X, 213, 0, Z), " & "210 (BC_0, LD(2), bidir, X, 213, 0, Z), " & "209 (BC_0, LD(3), bidir, X, 213, 0, Z), " & "208 (BC_0, LD(4), bidir, X, 213, 0, Z), " & "207 (BC_0, LD(5), bidir, X, 213, 0, Z), " & "206 (BC_0, LD(6), bidir, X, 213, 0, Z), " & "205 (BC_0, LD(7), bidir, X, 213, 0, Z), " & "204 (BC_0, LD(8), bidir, X, 213, 0, Z), " & "203 (BC_0, LD(9), bidir, X, 213, 0, Z), " & "202 (BC_0, LD(10), bidir, X, 213, 0, Z), " & "201 (BC_0, LD(11), bidir, X, 213, 0, Z), " & "200 (BC_0, LD(12), bidir, X, 213, 0, Z), " & "199 (BC_0, LD(13), bidir, X, 213, 0, Z), " & "198 (BC_0, LD(14), bidir, X, 213, 0, Z), " & "197 (BC_0, LD(15), bidir, X, 213, 0, Z), " & "196 (BC_1, LIM, input, X), " & "195 (BC_1, LMS, input, X), " & "194 (BC_2, LHOLD, output2, X), " & "193 (BC_1, LHLDA, input, X), " & "192 (BC_2, LBGACK, output2, X), " & "191 (BC_1, *, controlr, 0), " & "190 (BC_0, LINT, bidir, X, 191, 0, Z), " & "189 (BC_1, LCS, input, X), " & "188 (BC_1, LRDY, input, X), " & "187 (BC_2, LCLK, output2, X), " & "186 (BC_2, LBHE, output2, X), " & "185 (BC_1, *, controlr, 0), " & "184 (BC_0, LWR, bidir, X, 185, 0, Z), " & "183 (BC_1, *, controlr, 0), " & "182 (BC_0, LRD, bidir, X, 183, 0, Z), " & "181 (BC_1, *, controlr, 0), " & "180 (BC_0, LA(0), bidir, X, 181, 0, Z), " & "179 (BC_0, LA(1), bidir, X, 181, 0, Z), " & "178 (BC_0, LA(2), bidir, X, 181, 0, Z), " & "177 (BC_0, LA(3), bidir, X, 181, 0, Z), " & "176 (BC_0, LA(4), bidir, X, 181, 0, Z), " & "175 (BC_0, LA(5), bidir, X, 181, 0, Z), " & "174 (BC_0, LA(6), bidir, X, 181, 0, Z), " & "173 (BC_0, LA(7), bidir, X, 181, 0, Z), " & "172 (BC_0, LA(8), bidir, X, 181, 0, Z), " & "171 (BC_0, LA(9), bidir, X, 181, 0, Z), " & "170 (BC_0, LA(10), bidir, X, 181, 0, Z), " & "169 (BC_0, LA(11), bidir, X, 181, 0, Z), " & "168 (BC_0, LA(12), bidir, X, 181, 0, Z), " & "167 (BC_0, LA(13), bidir, X, 181, 0, Z), " & "166 (BC_0, LA(14), bidir, X, 181, 0, Z), " & "165 (BC_0, LA(15), bidir, X, 181, 0, Z), " & "164 (BC_0, LA(16), bidir, X, 181, 0, Z), " & "163 (BC_0, LA(17), bidir, X, 181, 0, Z), " & "162 (BC_0, LA(18), bidir, X, 181, 0, Z), " & "161 (BC_0, LA(19), bidir, X, 181, 0, Z), " & "160 (BC_1, RC(8), input, X), " & "159 (BC_1, RS(8), input, X), " & "158 (BC_1, RD(8), input, X), " & "157 (BC_1, TC(8), input, X), " & "156 (BC_1, TS(8), input, X), " & "155 (BC_2, TD(8), output2, X), " & "154 (BC_1, RC(9), input, X), " & "153 (BC_1, RS(9), input, X), " & "152 (BC_1, RD(9), input, X), " & "151 (BC_1, TC(9), input, X), " & "150 (BC_1, TS(9), input, X), " & "149 (BC_2, TD(9), output2, X), " & "148 (BC_1, RC(10), input, X), " & "147 (BC_1, RS(10), input, X), " & "146 (BC_1, RD(10), input, X), " & "145 (BC_1, TC(10), input, X), " & "144 (BC_1, TS(10), input, X), " & "143 (BC_2, TD(10), output2, X), " & "142 (BC_1, RC(11), input, X), " & "141 (BC_1, RS(11), input, X), " & "140 (BC_1, RD(11), input, X), " & "139 (BC_1, TC(11), input, X), " & "138 (BC_1, TS(11), input, X), " & "137 (BC_2, TD(11), output2, X), " & "136 (BC_1, RC(12), input, X), " & "135 (BC_1, RS(12), input, X), " & "134 (BC_1, RD(12), input, X), " & "133 (BC_1, TC(12), input, X), " & "132 (BC_1, TS(12), input, X), " & "131 (BC_2, TD(12), output2, X), " & "130 (BC_1, RC(13), input, X), " & "129 (BC_1, RS(13), input, X), " & "128 (BC_1, RD(13), input, X), " & "127 (BC_1, TC(13), input, X), " & "126 (BC_1, TS(13), input, X), " & "125 (BC_2, TD(13), output2, X), " & "124 (BC_1, RC(14), input, X), " & "123 (BC_1, RS(14), input, X), " & "122 (BC_1, RD(14), input, X), " & "121 (BC_1, TC(14), input, X), " & "120 (BC_1, TS(14), input, X), " & "119 (BC_2, TD(14), output2, X), " & "118 (BC_1, RC(15), input, X), " & "117 (BC_1, RS(15), input, X), " & "116 (BC_1, RD(15), input, X), " & "115 (BC_1, TC(15), input, X), " & "114 (BC_1, TS(15), input, X), " & "113 (BC_2, TD(15), output2, X), " & "112 (BC_1, RC(0), input, X), " & "111 (BC_1, RS(0), input, X), " & "110 (BC_1, RD(0), input, X), " & "109 (BC_1, TC(0), input, X), " & "108 (BC_1, TS(0), input, X), " & "107 (BC_2, TD(0), output2, X), " & "106 (BC_1, RC(1), input, X), " & "105 (BC_1, RS(1), input, X), " & "104 (BC_1, RD(1), input, X), " & "103 (BC_1, TC(1), input, X), " & "102 (BC_1, TS(1), input, X), " & "101 (BC_2, TD(1), output2, X), " & "100 (BC_1, RC(2), input, X), " & "99 (BC_1, RS(2), input, X), " & "98 (BC_1, RD(2), input, X), " & "97 (BC_1, TC(2), input, X), " & "96 (BC_1, TS(2), input, X), " & "95 (BC_2, TD(2), output2, X), " & "94 (BC_1, RC(3), input, X), " & "93 (BC_1, RS(3), input, X), " & "92 (BC_1, RD(3), input, X), " & "91 (BC_1, TC(3), input, X), " & "90 (BC_1, TS(3), input, X), " & "89 (BC_2, TD(3), output2, X), " & "88 (BC_1, RC(4), input, X), " & "87 (BC_1, RS(4), input, X), " & "86 (BC_1, RD(4), input, X), " & "85 (BC_1, TC(4), input, X), " & "84 (BC_1, TS(4), input, X), " & "83 (BC_2, TD(4), output2, X), " & "82 (BC_1, RC(5), input, X), " & "81 (BC_1, RS(5), input, X), " & "80 (BC_1, RD(5), input, X), " & "79 (BC_1, TC(5), input, X), " & "78 (BC_1, TS(5), input, X), " & "77 (BC_2, TD(5), output2, X), " & "76 (BC_1, RC(6), input, X), " & "75 (BC_1, RS(6), input, X), " & "74 (BC_1, RD(6), input, X), " & "73 (BC_1, TC(6), input, X), " & "72 (BC_1, TS(6), input, X), " & "71 (BC_2, TD(6), output2, X), " & "70 (BC_1, RC(7), input, X), " & "69 (BC_1, RS(7), input, X), " & "68 (BC_1, RD(7), input, X), " & "67 (BC_1, TC(7), input, X), " & "66 (BC_1, TS(7), input, X), " & "65 (BC_2, TD(7), output2, X), " & "64 (BC_1, PRST, input, X), " & "63 (BC_1, PCLK, input, X), " & "62 (BC_1, PGNT, input, X), " & "61 (BC_2, PREQ, output2, X), " & "60 (BC_1, *, controlr, 0), " & "59 (BC_0, PAD(31), bidir, X, 60, 0, Z), " & "58 (BC_0, PAD(30), bidir, X, 60, 0, Z), " & "57 (BC_0, PAD(29), bidir, X, 60, 0, Z), " & "56 (BC_0, PAD(28), bidir, X, 60, 0, Z), " & "55 (BC_0, PAD(27), bidir, X, 60, 0, Z), " & "54 (BC_0, PAD(26), bidir, X, 60, 0, Z), " & "53 (BC_0, PAD(25), bidir, X, 60, 0, Z), " & "52 (BC_0, PAD(24), bidir, X, 60, 0, Z), " & "51 (BC_1, *, controlr, 0), " & "50 (BC_0, PCBE(3), bidir, X, 51, 0, Z), " & "49 (BC_1, PIDSEL, input, X), " & "48 (BC_0, PAD(23), bidir, X, 60, 0, Z), " & "47 (BC_0, PAD(22), bidir, X, 60, 0, Z), " & "46 (BC_0, PAD(21), bidir, X, 60, 0, Z), " & "45 (BC_0, PAD(20), bidir, X, 60, 0, Z), " & "44 (BC_0, PAD(19), bidir, X, 60, 0, Z), " & "43 (BC_0, PAD(18), bidir, X, 60, 0, Z), " & "42 (BC_0, PAD(17), bidir, X, 60, 0, Z), " & "41 (BC_0, PAD(16), bidir, X, 60, 0, Z), " & "40 (BC_1, *, controlr, 0), " & "39 (BC_0, PCBE(2), bidir, X, 40, 0, Z), " & "38 (BC_1, *, controlr, 0), " & "37 (BC_0, PFRAME, bidir, X, 38, 0, Z), " & "36 (BC_1, *, controlr, 0), " & "35 (BC_0, PIRDY, bidir, X, 36, 0, Z), " & "34 (BC_1, *, controlr, 0), " & "33 (BC_0, PTRDY, bidir, X, 34, 0, Z), " & "32 (BC_1, *, controlr, 0), " & "31 (BC_0, PDEVSEL, bidir, X, 32, 0, Z), " & "30 (BC_1, *, controlr, 0), " & "29 (BC_0, PSTOP, bidir, X, 30, 0, Z), " & "28 (BC_1, *, controlr, 0), " & "27 (BC_0, PPERR, bidir, X, 28, 0, Z), " & "26 (BC_2, PSERR, output2, X), " & "25 (BC_1, *, controlr, 0), " & "24 (BC_0, PPAR, bidir, X, 25, 0, Z), " & "23 (BC_1, *, controlr, 0), " & "22 (BC_0, PCBE(1), bidir, X, 23, 0, Z), " & "21 (BC_0, PAD(15), bidir, X, 60, 0, Z), " & "20 (BC_0, PAD(14), bidir, X, 60, 0, Z), " & "19 (BC_0, PAD(13), bidir, X, 60, 0, Z), " & "18 (BC_0, PAD(12), bidir, X, 60, 0, Z), " & "17 (BC_0, PAD(11), bidir, X, 60, 0, Z), " & "16 (BC_0, PAD(10), bidir, X, 60, 0, Z), " & "15 (BC_0, PAD(9), bidir, X, 60, 0, Z), " & "14 (BC_0, PAD(8), bidir, X, 60, 0, Z), " & "13 (BC_1, *, controlr, 0), " & "12 (BC_0, PCBE(0), bidir, X, 13, 0, Z), " & "11 (BC_0, PAD(7), bidir, X, 60, 0, Z), " & "10 (BC_0, PAD(6), bidir, X, 60, 0, Z), " & "9 (BC_0, PAD(5), bidir, X, 60, 0, Z), " & "8 (BC_0, PAD(4), bidir, X, 60, 0, Z), " & "7 (BC_0, PAD(3), bidir, X, 60, 0, Z), " & "6 (BC_0, PAD(2), bidir, X, 60, 0, Z), " & "5 (BC_0, PAD(1), bidir, X, 60, 0, Z), " & "4 (BC_0, PAD(0), bidir, X, 60, 0, Z), " & "3 (BC_2, PINTA, output2, X), " & "2 (BC_2, PXAS, output2, X), " & "1 (BC_2, PXDS, output2, X), " & "0 (BC_2, PXBLAST, output2, X) "; end ds31256_top;