---------------------------------------------------------------------------------- -- -- File Name : DS26528CSBGA_BSDL.txt -- Created by Synopsys Version 2000.11 (Nov 27, 2000) -- -- Company : Dallas Semiconductor/Maxim -- Documentation : DS26528 datasheet -- BSDL Revision : 1.1 -- Date : 5/29/2007 -- -- Device : DS26528 -- Package : 256-pin CSBGA -- -- IMPORTANT NOTICE -- Dallas Semiconductor customers are advised to obtain the latest version of -- device specifications before relying on any published information contained -- herein. Dallas Semiconductor assumes no responsibility or liability arising -- out of the application of any information described herein. -- -- IMPORTANT NOTICE ABOUT THE REVISION -- -- Dallas Semiconductor customers are advised to check the revision of the -- device they will be using. All the codes for the device revisions are -- herein this BSDL file. -- -- The characters "/", "(", ")" and "*" have been removed from signal names for -- compatibility with BSDL file format. -- -- -------------------------------------------------------------------------------- entity dalsemi_ds26528 is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "CSBGA_256"); -- This section declares all the ports in the design. port ( bts : in bit; csb : in bit; digio_en : in bit; jtclk : in bit; jtdi : in bit; jtms : in bit; jtrst : in bit; mclk : in bit; rdb_dsb : in bit; resetb : in bit; rsysclk : in bit; scan_en : linkage bit; scan_mode : linkage bit; tsysclk : in bit; txen_b : in bit; wrb_rwb : in bit; a : in bit_vector (0 to 12); rring : linkage bit_vector (1 to 8); rtip : linkage bit_vector (1 to 8); tclk : in bit_vector (1 to 8); tser : in bit_vector (1 to 8); refclkio : inout bit; tssyncio : inout bit; d : inout bit_vector (0 to 7); rchblk_clk : inout bit_vector (1 to 8); rclk : inout bit_vector (1 to 8); rm_rfsync : inout bit_vector (1 to 8); rsig : inout bit_vector (1 to 8); rsync : inout bit_vector (1 to 8); tchblk_clk : inout bit_vector (1 to 8); tsig : inout bit_vector (1 to 8); tsync : inout bit_vector (1 to 8); bpclk : out bit; intb : out bit; jtdo : out bit; al_rsigf_flos : out bit_vector (1 to 8); rlf_ltc : out bit_vector (1 to 8); rser : out bit_vector (1 to 8); tring : linkage bit_vector (1 to 16); ttip : linkage bit_vector (1 to 16); VDD : linkage bit_vector (1 to 31); VSS : linkage bit_vector (1 to 31) ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of dalsemi_ds26528: entity is "STD_1149_1_1993"; attribute PIN_MAP of dalsemi_ds26528: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information -- is extracted from the port-to-pin map file that was read in using -- the "read_pin_map" command. constant CSBGA_256: PIN_MAP_STRING := "bts : M13," & "csb : T7," & "digio_en : D8," & "jtclk : F5," & "jtdi : H4," & "jtms : K4," & "jtrst : L5," & "mclk : B7," & "rdb_dsb : M8," & "resetb : J12," & "rsysclk : L12," & "scan_en : H12," & "scan_mode : H13," & "tsysclk : P13," & "txen_b : L13," & "wrb_rwb : R7," & "a : (C10, A10, B10, F9, E9, D9, C9, A9, B9, F8, B8, A8, C8)," & "rring : (C2, F2, L2, P2, P15, L15, F15, C15)," & "rtip : (C1, F1, L1, P1, P16, L16, F16, C16)," & "tclk : (C5, D7, P5, L8, L10, N11, E10, B13)," & "tser : (F6, E7, R4, N7, M10, L11, F10, D12)," & "refclkio : A7," & "tssyncio : N13," & "d : (N8, L9, P8, T8, R8, M9, N9, T9)," & "rchblk_clk : (E4, B5, L6, T5, T11, T13, C12, G13)," & "rclk : (F4, G4, L4, M4, K13, J13, F13, E13)," & "rm_rfsync : (C4, C6, P4, P6, P10, N12, D11, E12)," & "rsig : (D4, E6, M5, R5, R11, R13, A12, F12)," & "rsync : (A4, B6, N5, T6, R10, P12, C11, D13)," & "tchblk_clk : (A5, C7, L7, P7, P9, P11, D10, E11)," & "tsig : (D5, A6, T4, R6, T10, R12, A11, C13)," & "tsync : (B4, F7, M6, M7, N10, T12, B11, A13)," & "bpclk : E8," & "intb : R9," & "jtdo : J4," & "al_rsigf_flos : (C3, F3, L3, P3, P14, L14, F14, C14)," & "rlf_ltc : (D3, E3, M3, N3, N14, M14, E14, D14)," & "rser : (E5, D6, N4, N6, M11, M12, B12, F11)," & "tring : (A3, B3, G3, H3, J3, K3, R3, T3, R14, T14, J14, K14, G14, H14, A14, B14)," & "ttip : (A1, A2, H1, H2, J1, J2, T1, T2, T15, T16, J15, J16, H15, H16, A15, A16)," & "VDD : (D16, E16, M16, N16, N1, M1, E1, D1, H7, B16, G16, K16, R16, R1, K1, G1, B1, H8, H9, H11, H10, H6, H5, G9, G10, G11, G12, G5, G7, G6, G8)," & "VSS : (D15, E15, M15, N15, N2, M2, E2, D2, J7, B15, G15, K15, R15, R2, K2, G2, B2, J8, J9, J11, J10, J6, J5, K9, K10, K12, K11, K6, K5, K7, K8)"; -- This section specifies the TAP ports. -- For the TAP TCK port, the parameters in the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of jtclk: signal is (10.0e6, BOTH); attribute TAP_SCAN_IN of jtdi : signal is true; attribute TAP_SCAN_MODE of jtms : signal is true; attribute TAP_SCAN_OUT of jtdo : signal is true; attribute TAP_SCAN_RESET of jtrst: signal is true; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of dalsemi_ds26528: entity is 3; -- Specifies the boundary-scan instructions implemented in the -- design and their opcodes. attribute INSTRUCTION_OPCODE of dalsemi_ds26528: entity is "BYPASS (111)," & "EXTEST (000)," & "SAMPLE (010)," & "CLAMP (011)," & "USER1 (100)," & "USER2 (101)," & "USER3 (110)," & "IDCODE (001)"; -- Specifies the bit pattern that is loaded into the instruction -- register when the TAP controller passes through the Capture-IR -- state. The standard mandates that the two LSBs must be "01". -- The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of dalsemi_ds26528: entity is "001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID -- register during the IDCODE instruction when the TAP controller -- passes through the Capture-DR state. attribute IDCODE_REGISTER of dalsemi_ds26528: entity is "0010" & -- 4-bit version number for DS26528 Rev A3 "0000000000110111" & -- 16-bit part number "00010100001" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 -- This section specifies the test data register placed between TDI -- and TDO for each implemented instruction. attribute REGISTER_ACCESS of dalsemi_ds26528: entity is "BYPASS (BYPASS, CLAMP, USER1, USER2, USER3)," & "BOUNDARY (EXTEST, SAMPLE)," & "DEVICE_ID (IDCODE)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of dalsemi_ds26528: entity is 306; -- The following list specifies the characteristics of each cell -- in the boundary scan register from TDI to TDO. -- The following is a description of the label fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not -- have a port name. -- function: Is the function of the cell as defined by the -- standard. Is one of input, output2, output3, -- bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be -- loaded with for safe operation when the software -- might otherwise choose a random value. -- ccell : The control cell number. Specifies the control -- cell that drives the output enable for this port. -- disval : Specifies the value that is loaded into the -- control cell to disable the output enable for -- the corresponding port. -- rslt : Resulting state. Shows the state of the driver -- when it is disabled. attribute BOUNDARY_REGISTER of dalsemi_ds26528: entity is -- -- num cell port function safe [ccell disval rslt] -- "305 (BC_2, al_rsigf_flos(1), output3, X, 304, 1, Z), " & "304 (BC_2, *, controlr, 1), " & "303 (BC_2, rlf_ltc(1), output3, X, 302, 1, Z), " & "302 (BC_2, *, controlr, 1), " & "301 (BC_4, rsig(1), observe_only, X), " & "300 (BC_2, rsig(1), output3, X, 299, 1, Z), " & "299 (BC_2, *, controlr, 1), " & "298 (BC_4, rchblk_clk(1), observe_only, X), " & "297 (BC_2, rchblk_clk(1), output3, X, 296, 1, Z), " & "296 (BC_2, *, controlr, 1), " & "295 (BC_4, rclk(1), observe_only, X), " & "294 (BC_2, rclk(1), output3, X, 293, 1, Z), " & "293 (BC_2, *, controlr, 1), " & "292 (BC_4, rclk(2), observe_only, X), " & "291 (BC_2, rclk(2), output3, X, 290, 1, Z), " & "290 (BC_2, *, controlr, 1), " & "289 (BC_4, rclk(3), observe_only, X), " & "288 (BC_2, rclk(3), output3, X, 287, 1, Z), " & "287 (BC_2, *, controlr, 1), " & "286 (BC_4, rclk(4), observe_only, X), " & "285 (BC_2, rclk(4), output3, X, 284, 1, Z), " & "284 (BC_2, *, controlr, 1), " & "283 (BC_4, rchblk_clk(3), observe_only, X), " & "282 (BC_2, rchblk_clk(3), output3, X, 281, 1, Z), " & "281 (BC_2, *, controlr, 1), " & "280 (BC_4, rsig(3), observe_only, X), " & "279 (BC_2, rsig(3), output3, X, 278, 1, Z), " & "278 (BC_2, *, controlr, 1), " & "277 (BC_2, rlf_ltc(3), output3, X, 276, 1, Z), " & "276 (BC_2, *, controlr, 1), " & "275 (BC_2, al_rsigf_flos(3), output3, X, 274, 1, Z), " & "274 (BC_2, *, controlr, 1), " & "273 (BC_2, rser(3), output3, X, 272, 1, Z), " & "272 (BC_2, *, controlr, 1), " & "271 (BC_4, rm_rfsync(3), observe_only, X), " & "270 (BC_2, rm_rfsync(3), output3, X, 269, 1, Z), " & "269 (BC_2, *, controlr, 1), " & "268 (BC_4, rsync(3), observe_only, X), " & "267 (BC_2, rsync(3), output3, X, 266, 1, Z), " & "266 (BC_2, *, controlr, 1), " & "265 (BC_4, tsig(3), observe_only, X), " & "264 (BC_2, tsig(3), output3, X, 263, 1, Z), " & "263 (BC_2, *, controlr, 1), " & "262 (BC_4, tsync(3), observe_only, X), " & "261 (BC_2, tsync(3), output3, X, 260, 1, Z), " & "260 (BC_2, *, controlr, 1), " & "259 (BC_4, tser(3), observe_only, X), " & "258 (BC_4, tclk(3), observe_only, X), " & "257 (BC_4, tchblk_clk(3), observe_only, X), " & "256 (BC_2, tchblk_clk(3), output3, X, 255, 1, Z), " & "255 (BC_2, *, controlr, 1), " & "254 (BC_4, rchblk_clk(4), observe_only, X), " & "253 (BC_2, rchblk_clk(4), output3, X, 252, 1, Z), " & "252 (BC_2, *, controlr, 1), " & "251 (BC_4, rsig(4), observe_only, X), " & "250 (BC_2, rsig(4), output3, X, 249, 1, Z), " & "249 (BC_2, *, controlr, 1), " & "248 (BC_2, rlf_ltc(4), output3, X, 247, 1, Z), " & "247 (BC_2, *, controlr, 1), " & "246 (BC_2, al_rsigf_flos(4), output3, X, 245, 1, Z), " & "245 (BC_2, *, controlr, 1), " & "244 (BC_2, rser(4), output3, X, 243, 1, Z), " & "243 (BC_2, *, controlr, 1), " & "242 (BC_4, rm_rfsync(4), observe_only, X), " & "241 (BC_2, rm_rfsync(4), output3, X, 240, 1, Z), " & "240 (BC_2, *, controlr, 1), " & "239 (BC_4, rsync(4), observe_only, X), " & "238 (BC_2, rsync(4), output3, X, 237, 1, Z), " & "237 (BC_2, *, controlr, 1), " & "236 (BC_4, tsig(4), observe_only, X), " & "235 (BC_2, tsig(4), output3, X, 234, 1, Z), " & "234 (BC_2, *, controlr, 1), " & "233 (BC_4, tsync(4), observe_only, X), " & "232 (BC_2, tsync(4), output3, X, 231, 1, Z), " & "231 (BC_2, *, controlr, 1), " & "230 (BC_4, tser(4), observe_only, X), " & "229 (BC_4, tclk(4), observe_only, X), " & "228 (BC_4, tchblk_clk(4), observe_only, X), " & "227 (BC_2, tchblk_clk(4), output3, X, 226, 1, Z), " & "226 (BC_2, *, controlr, 1), " & "225 (BC_4, csb, observe_only, X), " & "224 (BC_4, wrb_rwb, observe_only, X), " & "223 (BC_4, rdb_dsb, observe_only, X), " & "222 (BC_4, d(0), observe_only, X), " & "221 (BC_2, d(0), output3, X, 220, 1, Z), " & "220 (BC_2, *, controlr, 1), " & "219 (BC_4, d(1), observe_only, X), " & "218 (BC_2, d(1), output3, X, 220, 1, Z), " & "217 (BC_4, d(2), observe_only, X), " & "216 (BC_2, d(2), output3, X, 220, 1, Z), " & "215 (BC_4, d(3), observe_only, X), " & "214 (BC_2, d(3), output3, X, 220, 1, Z), " & "213 (BC_4, d(4), observe_only, X), " & "212 (BC_2, d(4), output3, X, 220, 1, Z), " & "211 (BC_4, d(5), observe_only, X), " & "210 (BC_2, d(5), output3, X, 220, 1, Z), " & "209 (BC_4, d(6), observe_only, X), " & "208 (BC_2, d(6), output3, X, 220, 1, Z), " & "207 (BC_4, d(7), observe_only, X), " & "206 (BC_2, d(7), output3, X, 220, 1, Z), " & "205 (BC_2, intb, output3, X, 204, 1, WEAK1)," & "204 (BC_2, *, controlr, 1), " & "203 (BC_4, tchblk_clk(5), observe_only, X), " & "202 (BC_2, tchblk_clk(5), output3, X, 201, 1, Z), " & "201 (BC_2, *, controlr, 1), " & "200 (BC_4, tclk(5), observe_only, X), " & "199 (BC_4, tser(5), observe_only, X), " & "198 (BC_4, tsync(5), observe_only, X), " & "197 (BC_2, tsync(5), output3, X, 196, 1, Z), " & "196 (BC_2, *, controlr, 1), " & "195 (BC_4, tsig(5), observe_only, X), " & "194 (BC_2, tsig(5), output3, X, 193, 1, Z), " & "193 (BC_2, *, controlr, 1), " & "192 (BC_4, rsync(5), observe_only, X), " & "191 (BC_2, rsync(5), output3, X, 190, 1, Z), " & "190 (BC_2, *, controlr, 1), " & "189 (BC_4, rm_rfsync(5), observe_only, X), " & "188 (BC_2, rm_rfsync(5), output3, X, 187, 1, Z), " & "187 (BC_2, *, controlr, 1), " & "186 (BC_2, rser(5), output3, X, 185, 1, Z), " & "185 (BC_2, *, controlr, 1), " & "184 (BC_2, al_rsigf_flos(5), output3, X, 183, 1, Z), " & "183 (BC_2, *, controlr, 1), " & "182 (BC_2, rlf_ltc(5), output3, X, 181, 1, Z), " & "181 (BC_2, *, controlr, 1), " & "180 (BC_4, rsig(5), observe_only, X), " & "179 (BC_2, rsig(5), output3, X, 178, 1, Z), " & "178 (BC_2, *, controlr, 1), " & "177 (BC_4, rchblk_clk(5), observe_only, X), " & "176 (BC_2, rchblk_clk(5), output3, X, 175, 1, Z), " & "175 (BC_2, *, controlr, 1), " & "174 (BC_4, tchblk_clk(6), observe_only, X), " & "173 (BC_2, tchblk_clk(6), output3, X, 172, 1, Z), " & "172 (BC_2, *, controlr, 1), " & "171 (BC_4, tclk(6), observe_only, X), " & "170 (BC_4, tser(6), observe_only, X), " & "169 (BC_4, tsync(6), observe_only, X), " & "168 (BC_2, tsync(6), output3, X, 167, 1, Z), " & "167 (BC_2, *, controlr, 1), " & "166 (BC_4, tsig(6), observe_only, X), " & "165 (BC_2, tsig(6), output3, X, 164, 1, Z), " & "164 (BC_2, *, controlr, 1), " & "163 (BC_4, rsync(6), observe_only, X), " & "162 (BC_2, rsync(6), output3, X, 161, 1, Z), " & "161 (BC_2, *, controlr, 1), " & "160 (BC_4, rm_rfsync(6), observe_only, X), " & "159 (BC_2, rm_rfsync(6), output3, X, 158, 1, Z), " & "158 (BC_2, *, controlr, 1), " & "157 (BC_2, rser(6), output3, X, 156, 1, Z), " & "156 (BC_2, *, controlr, 1), " & "155 (BC_2, al_rsigf_flos(6), output3, X, 154, 1, Z), " & "154 (BC_2, *, controlr, 1), " & "153 (BC_2, rlf_ltc(6), output3, X, 152, 1, Z), " & "152 (BC_2, *, controlr, 1), " & "151 (BC_4, rsig(6), observe_only, X), " & "150 (BC_2, rsig(6), output3, X, 149, 1, Z), " & "149 (BC_2, *, controlr, 1), " & "148 (BC_4, rchblk_clk(6), observe_only, X), " & "147 (BC_2, rchblk_clk(6), output3, X, 146, 1, Z), " & "146 (BC_2, *, controlr, 1), " & "145 (BC_4, tsysclk, observe_only, X), " & "144 (BC_4, tssyncio, observe_only, X), " & "143 (BC_2, tssyncio, output3, X, 142, 1, Z), " & "142 (BC_2, *, controlr, 1), " & "141 (BC_4, rsysclk, observe_only, X), " & "140 (BC_4, bts, observe_only, X), " & "139 (BC_4, txen_b, observe_only, X), " & "138 (BC_4, resetb, observe_only, X), " & "137 (BC_4, rclk(5), observe_only, X), " & "136 (BC_2, rclk(5), output3, X, 135, 1, Z), " & "135 (BC_2, *, controlr, 1), " & "134 (BC_4, rclk(6), observe_only, X), " & "133 (BC_2, rclk(6), output3, X, 132, 1, Z), " & "132 (BC_2, *, controlr, 1), " & "131 (BC_4, rchblk_clk(8), observe_only, X), " & "130 (BC_2, rchblk_clk(8), output3, X, 129, 1, Z), " & "129 (BC_2, *, controlr, 1), " & "128 (BC_4, rsig(8), observe_only, X), " & "127 (BC_2, rsig(8), output3, X, 126, 1, Z), " & "126 (BC_2, *, controlr, 1), " & "125 (BC_4, rclk(7), observe_only, X), " & "124 (BC_2, rclk(7), output3, X, 123, 1, Z), " & "123 (BC_2, *, controlr, 1), " & "122 (BC_4, rclk(8), observe_only, X), " & "121 (BC_2, rclk(8), output3, X, 120, 1, Z), " & "120 (BC_2, *, controlr, 1), " & "119 (BC_2, rlf_ltc(8), output3, X, 118, 1, Z), " & "118 (BC_2, *, controlr, 1), " & "117 (BC_2, al_rsigf_flos(8), output3, X, 116, 1, Z), " & "116 (BC_2, *, controlr, 1), " & "115 (BC_2, rser(8), output3, X, 114, 1, Z), " & "114 (BC_2, *, controlr, 1), " & "113 (BC_4, rm_rfsync(8), observe_only, X), " & "112 (BC_2, rm_rfsync(8), output3, X, 111, 1, Z), " & "111 (BC_2, *, controlr, 1), " & "110 (BC_4, rsync(8), observe_only, X), " & "109 (BC_2, rsync(8), output3, X, 108, 1, Z), " & "108 (BC_2, *, controlr, 1), " & "107 (BC_4, tsig(8), observe_only, X), " & "106 (BC_2, tsig(8), output3, X, 105, 1, Z), " & "105 (BC_2, *, controlr, 1), " & "104 (BC_4, tsync(8), observe_only, X), " & "103 (BC_2, tsync(8), output3, X, 102, 1, Z), " & "102 (BC_2, *, controlr, 1), " & "101 (BC_4, tser(8), observe_only, X), " & "100 (BC_4, tclk(8), observe_only, X), " & "99 (BC_4, tchblk_clk(8), observe_only, X), " & "98 (BC_2, tchblk_clk(8), output3, X, 97, 1, Z), " & "97 (BC_2, *, controlr, 1), " & "96 (BC_4, rchblk_clk(7), observe_only, X), " & "95 (BC_2, rchblk_clk(7), output3, X, 94, 1, Z), " & "94 (BC_2, *, controlr, 1), " & "93 (BC_4, rsig(7), observe_only, X), " & "92 (BC_2, rsig(7), output3, X, 91, 1, Z), " & "91 (BC_2, *, controlr, 1), " & "90 (BC_2, rlf_ltc(7), output3, X, 89, 1, Z), " & "89 (BC_2, *, controlr, 1), " & "88 (BC_2, al_rsigf_flos(7), output3, X, 87, 1, Z), " & "87 (BC_2, *, controlr, 1), " & "86 (BC_2, rser(7), output3, X, 85, 1, Z), " & "85 (BC_2, *, controlr, 1), " & "84 (BC_4, rm_rfsync(7), observe_only, X), " & "83 (BC_2, rm_rfsync(7), output3, X, 82, 1, Z), " & "82 (BC_2, *, controlr, 1), " & "81 (BC_4, rsync(7), observe_only, X), " & "80 (BC_2, rsync(7), output3, X, 79, 1, Z), " & "79 (BC_2, *, controlr, 1), " & "78 (BC_4, tsig(7), observe_only, X), " & "77 (BC_2, tsig(7), output3, X, 76, 1, Z), " & "76 (BC_2, *, controlr, 1), " & "75 (BC_4, tsync(7), observe_only, X), " & "74 (BC_2, tsync(7), output3, X, 73, 1, Z), " & "73 (BC_2, *, controlr, 1), " & "72 (BC_4, tser(7), observe_only, X), " & "71 (BC_4, tclk(7), observe_only, X), " & "70 (BC_4, tchblk_clk(7), observe_only, X), " & "69 (BC_2, tchblk_clk(7), output3, X, 68, 1, Z), " & "68 (BC_2, *, controlr, 1), " & "67 (BC_4, a(0), observe_only, X), " & "66 (BC_4, a(1), observe_only, X), " & "65 (BC_4, a(2), observe_only, X), " & "64 (BC_4, a(3), observe_only, X), " & "63 (BC_4, a(4), observe_only, X), " & "62 (BC_4, a(5), observe_only, X), " & "61 (BC_4, a(6), observe_only, X), " & "60 (BC_4, a(7), observe_only, X), " & "59 (BC_4, a(8), observe_only, X), " & "58 (BC_4, a(9), observe_only, X), " & "57 (BC_4, digio_en, observe_only, X), " & "56 (BC_4, a(10), observe_only, X), " & "55 (BC_4, a(11), observe_only, X), " & "54 (BC_4, a(12), observe_only, X), " & "53 (BC_2, bpclk, output3, X, 52, 1, Z), " & "52 (BC_2, *, controlr, 1), " & "51 (BC_4, refclkio, observe_only, X), " & "50 (BC_2, refclkio, output3, X, 49, 1, Z), " & "49 (BC_2, *, controlr, 1), " & "48 (BC_4, mclk, observe_only, X), " & "47 (BC_4, tchblk_clk(2), observe_only, X), " & "46 (BC_2, tchblk_clk(2), output3, X, 45, 1, Z), " & "45 (BC_2, *, controlr, 1), " & "44 (BC_4, tclk(2), observe_only, X), " & "43 (BC_4, tser(2), observe_only, X), " & "42 (BC_4, tsync(2), observe_only, X), " & "41 (BC_2, tsync(2), output3, X, 40, 1, Z), " & "40 (BC_2, *, controlr, 1), " & "39 (BC_4, tsig(2), observe_only, X), " & "38 (BC_2, tsig(2), output3, X, 37, 1, Z), " & "37 (BC_2, *, controlr, 1), " & "36 (BC_4, rsync(2), observe_only, X), " & "35 (BC_2, rsync(2), output3, X, 34, 1, Z), " & "34 (BC_2, *, controlr, 1), " & "33 (BC_4, rm_rfsync(2), observe_only, X), " & "32 (BC_2, rm_rfsync(2), output3, X, 31, 1, Z), " & "31 (BC_2, *, controlr, 1), " & "30 (BC_2, rser(2), output3, X, 29, 1, Z), " & "29 (BC_2, *, controlr, 1), " & "28 (BC_2, al_rsigf_flos(2), output3, X, 27, 1, Z), " & "27 (BC_2, *, controlr, 1), " & "26 (BC_2, rlf_ltc(2), output3, X, 25, 1, Z), " & "25 (BC_2, *, controlr, 1), " & "24 (BC_4, rsig(2), observe_only, X), " & "23 (BC_2, rsig(2), output3, X, 22, 1, Z), " & "22 (BC_2, *, controlr, 1), " & "21 (BC_4, rchblk_clk(2), observe_only, X), " & "20 (BC_2, rchblk_clk(2), output3, X, 19, 1, Z), " & "19 (BC_2, *, controlr, 1), " & "18 (BC_4, tchblk_clk(1), observe_only, X), " & "17 (BC_2, tchblk_clk(1), output3, X, 16, 1, Z), " & "16 (BC_2, *, controlr, 1), " & "15 (BC_4, tclk(1), observe_only, X), " & "14 (BC_4, tser(1), observe_only, X), " & "13 (BC_4, tsync(1), observe_only, X), " & "12 (BC_2, tsync(1), output3, X, 11, 1, Z), " & "11 (BC_2, *, controlr, 1), " & "10 (BC_4, tsig(1), observe_only, X), " & "9 (BC_2, tsig(1), output3, X, 8, 1, Z), " & "8 (BC_2, *, controlr, 1), " & "7 (BC_4, rsync(1), observe_only, X), " & "6 (BC_2, rsync(1), output3, X, 5, 1, Z), " & "5 (BC_2, *, controlr, 1), " & "4 (BC_4, rm_rfsync(1), observe_only, X), " & "3 (BC_2, rm_rfsync(1), output3, X, 2, 1, Z), " & "2 (BC_2, *, controlr, 1), " & "1 (BC_2, rser(1), output3, X, 0, 1, Z), " & "0 (BC_2, *, controlr, 1) "; end dalsemi_ds26528;