-- *********************************************************************** -- BSDL file for design ds26514 -- Created by Synopsys Version 2000.11 (Nov 27, 2000) -- Designer: -- Company: -- Date: Wed Jun 27 18:01:13 2007 -- *********************************************************************** entity ds26514 is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "LBGA_256"); -- This section declares all the ports in the design. port ( HIZ_N : in bit; JTCLK : in bit; JTDI : in bit; JTMS : in bit; JTRST_N : in bit; SCAN_MODE : in bit; A0 : inout bit; A1 : inout bit; A10 : inout bit; A11 : inout bit; A12 : inout bit; A2 : inout bit; A3 : inout bit; A4 : inout bit; A5 : inout bit; A6 : inout bit; A7 : inout bit; A8 : inout bit; A9 : inout bit; BPCLK : inout bit; BTS : inout bit; CLKO : inout bit; CSB : inout bit; D0 : inout bit; D1 : inout bit; D2 : inout bit; D3 : inout bit; D4 : inout bit; D5 : inout bit; D6 : inout bit; D7 : inout bit; INTB : inout bit; MCLK : inout bit; RCHBLK1 : inout bit; RCHBLK2 : inout bit; RCHBLK3 : inout bit; RCHBLK4 : inout bit; RCLK1 : inout bit; RCLK2 : inout bit; RCLK3 : inout bit; RCLK4 : inout bit; RDB : inout bit; REFCLKIO : inout bit; RESETB : inout bit; RESREF : inout bit; RMSYNC1 : inout bit; RMSYNC2 : inout bit; RMSYNC3 : inout bit; RMSYNC4 : inout bit; RRING1 : inout bit; RRING2 : inout bit; RRING3 : inout bit; RRING4 : inout bit; RSER1 : inout bit; RSER2 : inout bit; RSER3 : inout bit; RSER4 : inout bit; RSIG1 : inout bit; RSIG2 : inout bit; RSIG3 : inout bit; RSIG4 : inout bit; RSYNC1 : inout bit; RSYNC2 : inout bit; RSYNC3 : inout bit; RSYNC4 : inout bit; RSYSCLK1 : inout bit; RSYSCLK2 : inout bit; RSYSCLK3 : inout bit; RSYSCLK4 : inout bit; RTIP1 : inout bit; RTIP2 : inout bit; RTIP3 : inout bit; RTIP4 : inout bit; SPI_SEL : inout bit; TCHBLK1 : inout bit; TCHBLK2 : inout bit; TCHBLK3 : inout bit; TCHBLK4 : inout bit; TCLK1 : inout bit; TCLK2 : inout bit; TCLK3 : inout bit; TCLK4 : inout bit; TSER1 : inout bit; TSER2 : inout bit; TSER3 : inout bit; TSER4 : inout bit; TSIG1 : inout bit; TSIG2 : inout bit; TSIG3 : inout bit; TSIG4 : inout bit; TSSYNC : inout bit; TSYNC1 : inout bit; TSYNC2 : inout bit; TSYNC3 : inout bit; TSYNC4 : inout bit; TSYSCLK1 : inout bit; TSYSCLK2 : inout bit; TSYSCLK3 : inout bit; TSYSCLK4 : inout bit; TX_ENABLE : inout bit; WRB : inout bit; TRING1 : inout bit_vector (0 to 1); TRING2 : inout bit_vector (0 to 1); TRING3 : inout bit_vector (0 to 1); TRING4 : inout bit_vector (0 to 1); TTIP1 : inout bit_vector (0 to 1); TTIP2 : inout bit_vector (0 to 1); TTIP3 : inout bit_vector (0 to 1); TTIP4 : inout bit_vector (0 to 1); JTDO : out bit; VDD18 : linkage bit_vector (1 to 5); VDD33 : linkage bit_vector (1 to 26); VSS : linkage bit_vector (1 to 31) ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of ds26514: entity is "STD_1149_1_1993"; attribute PIN_MAP of ds26514: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information -- is extracted from the port-to-pin map file that was read in using -- the "read_pin_map" command. constant LBGA_256: PIN_MAP_STRING := "HIZ_N : D8," & "JTCLK : F5," & "JTDI : H4," & "JTMS : K4," & "JTRST_N : L5," & "SCAN_MODE : H13," & "A0 : C10," & "A1 : A10," & "A10 : B8," & "A11 : A8," & "A12 : C8," & "A2 : B10," & "A3 : F9," & "A4 : E9," & "A5 : D9," & "A6 : C9," & "A7 : A9," & "A8 : B9," & "A9 : F8," & "BPCLK : E8," & "BTS : M13," & "CLKO : D3," & "CSB : T7," & "D0 : N8," & "D1 : L9," & "D2 : P8," & "D3 : T8," & "D4 : R8," & "D5 : M9," & "D6 : N9," & "D7 : T9," & "INTB : R9," & "MCLK : B7," & "RCHBLK1 : E4," & "RCHBLK2 : B5," & "RCHBLK3 : L6," & "RCHBLK4 : T5," & "RCLK1 : F4," & "RCLK2 : G4," & "RCLK3 : L4," & "RCLK4 : M4," & "RDB : M8," & "REFCLKIO : A7," & "RESETB : J12," & "RESREF : J5," & "RMSYNC1 : C4," & "RMSYNC2 : C6," & "RMSYNC3 : P4," & "RMSYNC4 : P6," & "RRING1 : C2," & "RRING2 : F2," & "RRING3 : L2," & "RRING4 : P2," & "RSER1 : E5," & "RSER2 : D6," & "RSER3 : N4," & "RSER4 : N6," & "RSIG1 : D4," & "RSIG2 : E6," & "RSIG3 : M5," & "RSIG4 : R5," & "RSYNC1 : A4," & "RSYNC2 : B6," & "RSYNC3 : N5," & "RSYNC4 : T6," & "RSYSCLK1 : L12," & "RSYSCLK2 : E3," & "RSYSCLK3 : M3," & "RSYSCLK4 : N3," & "RTIP1 : C1," & "RTIP2 : F1," & "RTIP3 : L1," & "RTIP4 : P1," & "SPI_SEL : C3," & "TCHBLK1 : A5," & "TCHBLK2 : C7," & "TCHBLK3 : L7," & "TCHBLK4 : P7," & "TCLK1 : C5," & "TCLK2 : D7," & "TCLK3 : P5," & "TCLK4 : L8," & "TSER1 : F6," & "TSER2 : E7," & "TSER3 : R4," & "TSER4 : N7," & "TSIG1 : D5," & "TSIG2 : A6," & "TSIG3 : T4," & "TSIG4 : R6," & "TSSYNC : N13," & "TSYNC1 : B4," & "TSYNC2 : F7," & "TSYNC3 : M6," & "TSYNC4 : M7," & "TSYSCLK1 : P13," & "TSYSCLK2 : F3," & "TSYSCLK3 : L3," & "TSYSCLK4 : P3," & "TX_ENABLE : L13," & "WRB : R7," & "TRING1 : (B3, A3)," & "TRING2 : (H3, G3)," & "TRING3 : (K3, J3)," & "TRING4 : (T3, R3)," & "TTIP1 : (A2, A1)," & "TTIP2 : (H2, H1)," & "TTIP3 : (J2, J1)," & "TTIP4 : (T2, T1)," & "JTDO : J4," & "VDD18 : (G7, G8, G9, G10, H7)," & "VDD33 : (D16, E16, M16, N16, N1, M1, E1, D1, B16, G16, K16, R16" & ", R1, K1, G1, B1, H8, H9, H11, H10, H6, H5, G11, G12, G5, G6)," & "VSS : (D15, E15, M15, N15, N2, M2, E2, D2, J7, B15, G15, K15" & ", R15, R2, K2, G2, B2, J8, J9, J11, J10, J6, K9, K10, K12, K11, K6" & ", K5, K7, K8, H12)"; -- This section specifies the TAP ports. -- For the TAP TCK port, the parameters in the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of JTCLK : signal is (10.0e6, BOTH); attribute TAP_SCAN_IN of JTDI : signal is true; attribute TAP_SCAN_MODE of JTMS : signal is true; attribute TAP_SCAN_OUT of JTDO : signal is true; attribute TAP_SCAN_RESET of JTRST_N: signal is true; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of ds26514: entity is 3; -- Specifies the boundary-scan instructions implemented in the -- design and their opcodes. attribute INSTRUCTION_OPCODE of ds26514: entity is "BYPASS (111)," & "EXTEST (000)," & "SAMPLE (010)," & "USER1 (100)," & "IDCODE (001)"; -- Specifies the bit pattern that is loaded into the instruction -- register when the TAP controller passes through the Capture-IR -- state. The standard mandates that the two LSBs must be "01". -- The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of ds26514: entity is "001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID -- register during the IDCODE instruction when the TAP controller -- passes through the Capture-DR state. attribute IDCODE_REGISTER of ds26514: entity is "0010" & -- 4-bit version number "0000000010001100" & -- 16-bit part number "00010100001" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 -- This section specifies the test data register placed between TDI -- and TDO for each implemented instruction. attribute REGISTER_ACCESS of ds26514: entity is "BYPASS (BYPASS, USER1)," & "BOUNDARY (EXTEST, SAMPLE)," & "DEVICE_ID (IDCODE)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of ds26514: entity is 268; -- The following list specifies the characteristics of each cell -- in the boundary scan register from TDI to TDO. -- The following is a description of the label fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not -- have a port name. -- function: Is the function of the cell as defined by the -- standard. Is one of input, output2, output3, -- bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be -- loaded with for safe operation when the software -- might otherwise choose a random value. -- ccell : The control cell number. Specifies the control -- cell that drives the output enable for this port. -- disval : Specifies the value that is loaded into the -- control cell to disable the output enable for -- the corresponding port. -- rslt : Resulting state. Shows the state of the driver -- when it is disabled. attribute BOUNDARY_REGISTER of ds26514: entity is -- -- num cell port function safe [ccell disval rslt] -- "267 (BC_1, *, controlr, 0), " & "266 (BC_0, RCHBLK3, bidir, X, 267, 0, Z), " & "265 (BC_1, *, controlr, 0), " & "264 (BC_0, RSIG3, bidir, X, 265, 0, Z), " & "263 (BC_1, *, controlr, 0), " & "262 (BC_0, RSYSCLK3, bidir, X, 263, 0, PULL0)," & "261 (BC_1, *, controlr, 0), " & "260 (BC_0, TSYSCLK3, bidir, X, 261, 0, PULL0)," & "259 (BC_1, *, controlr, 0), " & "258 (BC_0, RSER3, bidir, X, 259, 0, Z), " & "257 (BC_1, *, controlr, 0), " & "256 (BC_0, RMSYNC3, bidir, X, 257, 0, Z), " & "255 (BC_1, *, controlr, 0), " & "254 (BC_0, RSYNC3, bidir, X, 255, 0, Z), " & "253 (BC_1, *, controlr, 0), " & "252 (BC_0, TSIG3, bidir, X, 253, 0, Z), " & "251 (BC_1, *, controlr, 0), " & "250 (BC_0, TSYNC3, bidir, X, 251, 0, Z), " & "249 (BC_1, *, controlr, 0), " & "248 (BC_0, TSER3, bidir, X, 249, 0, Z), " & "247 (BC_1, *, controlr, 0), " & "246 (BC_0, TCLK3, bidir, X, 247, 0, Z), " & "245 (BC_1, *, controlr, 0), " & "244 (BC_0, TCHBLK3, bidir, X, 245, 0, Z), " & "243 (BC_1, *, controlr, 0), " & "242 (BC_0, RCHBLK4, bidir, X, 243, 0, Z), " & "241 (BC_1, *, controlr, 0), " & "240 (BC_0, RSIG4, bidir, X, 241, 0, Z), " & "239 (BC_1, *, controlr, 0), " & "238 (BC_0, RSYSCLK4, bidir, X, 239, 0, PULL0)," & "237 (BC_1, *, controlr, 0), " & "236 (BC_0, TSYSCLK4, bidir, X, 237, 0, PULL0)," & "235 (BC_1, *, controlr, 0), " & "234 (BC_0, RSER4, bidir, X, 235, 0, Z), " & "233 (BC_1, *, controlr, 0), " & "232 (BC_0, RMSYNC4, bidir, X, 233, 0, Z), " & "231 (BC_1, *, controlr, 0), " & "230 (BC_0, RSYNC4, bidir, X, 231, 0, Z), " & "229 (BC_1, *, controlr, 0), " & "228 (BC_0, TSIG4, bidir, X, 229, 0, Z), " & "227 (BC_1, *, controlr, 0), " & "226 (BC_0, TSYNC4, bidir, X, 227, 0, Z), " & "225 (BC_1, *, controlr, 0), " & "224 (BC_0, TSER4, bidir, X, 225, 0, Z), " & "223 (BC_1, *, controlr, 0), " & "222 (BC_0, TCLK4, bidir, X, 223, 0, Z), " & "221 (BC_1, *, controlr, 0), " & "220 (BC_0, TCHBLK4, bidir, X, 221, 0, Z), " & "219 (BC_1, *, controlr, 0), " & "218 (BC_0, CSB, bidir, X, 219, 0, Z), " & "217 (BC_1, *, controlr, 0), " & "216 (BC_0, WRB, bidir, X, 217, 0, Z), " & "215 (BC_1, *, controlr, 0), " & "214 (BC_0, RDB, bidir, X, 215, 0, Z), " & "213 (BC_1, *, controlr, 0), " & "212 (BC_0, D0, bidir, X, 213, 0, Z), " & "211 (BC_1, *, controlr, 0), " & "210 (BC_0, D1, bidir, X, 211, 0, Z), " & "209 (BC_1, *, controlr, 0), " & "208 (BC_0, D2, bidir, X, 209, 0, Z), " & "207 (BC_1, *, controlr, 0), " & "206 (BC_0, D3, bidir, X, 207, 0, Z), " & "205 (BC_1, *, controlr, 0), " & "204 (BC_0, D4, bidir, X, 205, 0, Z), " & "203 (BC_1, *, controlr, 0), " & "202 (BC_0, D5, bidir, X, 203, 0, Z), " & "201 (BC_1, *, controlr, 0), " & "200 (BC_0, D6, bidir, X, 201, 0, Z), " & "199 (BC_1, *, controlr, 0), " & "198 (BC_0, D7, bidir, X, 199, 0, Z), " & "197 (BC_1, *, controlr, 0), " & "196 (BC_0, INTB, bidir, X, 197, 0, Z), " & "195 (BC_0, *, internal, X), " & "194 (BC_0, *, internal, X), " & "193 (BC_0, *, internal, X), " & "192 (BC_0, *, internal, X), " & "191 (BC_0, *, internal, X), " & "190 (BC_0, *, internal, X), " & "189 (BC_0, *, internal, X), " & "188 (BC_0, *, internal, X), " & "187 (BC_0, *, internal, X), " & "186 (BC_0, *, internal, X), " & "185 (BC_0, *, internal, X), " & "184 (BC_0, *, internal, X), " & "183 (BC_0, *, internal, X), " & "182 (BC_0, *, internal, X), " & "181 (BC_0, *, internal, X), " & "180 (BC_0, *, internal, X), " & "179 (BC_0, *, internal, X), " & "178 (BC_0, *, internal, X), " & "177 (BC_0, *, internal, X), " & "176 (BC_0, *, internal, X), " & "175 (BC_0, *, internal, X), " & "174 (BC_0, *, internal, X), " & "173 (BC_0, *, internal, X), " & "172 (BC_0, *, internal, X), " & "171 (BC_0, *, internal, X), " & "170 (BC_0, *, internal, X), " & "169 (BC_0, *, internal, X), " & "168 (BC_0, *, internal, X), " & "167 (BC_0, *, internal, X), " & "166 (BC_0, *, internal, X), " & "165 (BC_0, *, internal, X), " & "164 (BC_0, *, internal, X), " & "163 (BC_0, *, internal, X), " & "162 (BC_0, *, internal, X), " & "161 (BC_0, *, internal, X), " & "160 (BC_0, *, internal, X), " & "159 (BC_0, *, internal, X), " & "158 (BC_0, *, internal, X), " & "157 (BC_0, *, internal, X), " & "156 (BC_0, *, internal, X), " & "155 (BC_0, *, internal, X), " & "154 (BC_0, *, internal, X), " & "153 (BC_0, *, internal, X), " & "152 (BC_0, *, internal, X), " & "151 (BC_0, *, internal, X), " & "150 (BC_0, *, internal, X), " & "149 (BC_0, *, internal, X), " & "148 (BC_0, *, internal, X), " & "147 (BC_1, *, controlr, 0), " & "146 (BC_0, TSYSCLK1, bidir, X, 147, 0, Z), " & "145 (BC_1, *, controlr, 0), " & "144 (BC_0, TSSYNC, bidir, X, 145, 0, Z), " & "143 (BC_1, *, controlr, 0), " & "142 (BC_0, RSYSCLK1, bidir, X, 143, 0, Z), " & "141 (BC_1, *, controlr, 0), " & "140 (BC_0, BTS, bidir, X, 141, 0, Z), " & "139 (BC_1, *, controlr, 0), " & "138 (BC_0, TX_ENABLE, bidir, X, 139, 0, Z), " & "137 (BC_1, *, controlr, 0), " & "136 (BC_0, RESETB, bidir, X, 137, 0, Z), " & "135 (BC_0, *, internal, X), " & "134 (BC_0, *, internal, X), " & "133 (BC_0, *, internal, X), " & "132 (BC_0, *, internal, X), " & "131 (BC_0, *, internal, X), " & "130 (BC_0, *, internal, X), " & "129 (BC_0, *, internal, X), " & "128 (BC_0, *, internal, X), " & "127 (BC_0, *, internal, X), " & "126 (BC_0, *, internal, X), " & "125 (BC_0, *, internal, X), " & "124 (BC_0, *, internal, X), " & "123 (BC_0, *, internal, X), " & "122 (BC_0, *, internal, X), " & "121 (BC_0, *, internal, X), " & "120 (BC_0, *, internal, X), " & "119 (BC_0, *, internal, X), " & "118 (BC_0, *, internal, X), " & "117 (BC_0, *, internal, X), " & "116 (BC_0, *, internal, X), " & "115 (BC_0, *, internal, X), " & "114 (BC_0, *, internal, X), " & "113 (BC_0, *, internal, X), " & "112 (BC_0, *, internal, X), " & "111 (BC_0, *, internal, X), " & "110 (BC_0, *, internal, X), " & "109 (BC_0, *, internal, X), " & "108 (BC_0, *, internal, X), " & "107 (BC_0, *, internal, X), " & "106 (BC_0, *, internal, X), " & "105 (BC_0, *, internal, X), " & "104 (BC_0, *, internal, X), " & "103 (BC_0, *, internal, X), " & "102 (BC_0, *, internal, X), " & "101 (BC_0, *, internal, X), " & "100 (BC_0, *, internal, X), " & "99 (BC_0, *, internal, X), " & "98 (BC_0, *, internal, X), " & "97 (BC_0, *, internal, X), " & "96 (BC_0, *, internal, X), " & "95 (BC_0, *, internal, X), " & "94 (BC_0, *, internal, X), " & "93 (BC_0, *, internal, X), " & "92 (BC_0, *, internal, X), " & "91 (BC_0, *, internal, X), " & "90 (BC_0, *, internal, X), " & "89 (BC_0, *, internal, X), " & "88 (BC_0, *, internal, X), " & "87 (BC_0, *, internal, X), " & "86 (BC_0, *, internal, X), " & "85 (BC_0, *, internal, X), " & "84 (BC_0, *, internal, X), " & "83 (BC_0, *, internal, X), " & "82 (BC_0, *, internal, X), " & "81 (BC_0, *, internal, X), " & "80 (BC_0, *, internal, X), " & "79 (BC_1, *, controlr, 0), " & "78 (BC_0, A0, bidir, X, 79, 0, Z), " & "77 (BC_1, *, controlr, 0), " & "76 (BC_0, A1, bidir, X, 77, 0, Z), " & "75 (BC_1, *, controlr, 0), " & "74 (BC_0, A2, bidir, X, 75, 0, Z), " & "73 (BC_1, *, controlr, 0), " & "72 (BC_0, A3, bidir, X, 73, 0, Z), " & "71 (BC_1, *, controlr, 0), " & "70 (BC_0, A4, bidir, X, 71, 0, Z), " & "69 (BC_1, *, controlr, 0), " & "68 (BC_0, A5, bidir, X, 69, 0, Z), " & "67 (BC_1, *, controlr, 0), " & "66 (BC_0, A6, bidir, X, 67, 0, Z), " & "65 (BC_1, *, controlr, 0), " & "64 (BC_0, A7, bidir, X, 65, 0, Z), " & "63 (BC_1, *, controlr, 0), " & "62 (BC_0, A8, bidir, X, 63, 0, Z), " & "61 (BC_1, *, controlr, 0), " & "60 (BC_0, A9, bidir, X, 61, 0, Z), " & "59 (BC_1, *, controlr, 0), " & "58 (BC_0, A10, bidir, X, 59, 0, Z), " & "57 (BC_1, *, controlr, 0), " & "56 (BC_0, A11, bidir, X, 57, 0, Z), " & "55 (BC_1, *, controlr, 0), " & "54 (BC_0, TCHBLK2, bidir, X, 55, 0, Z), " & "53 (BC_1, *, controlr, 0), " & "52 (BC_0, MCLK, bidir, X, 53, 0, Z), " & "51 (BC_1, *, controlr, 0), " & "50 (BC_0, REFCLKIO, bidir, X, 51, 0, Z), " & "49 (BC_1, *, controlr, 0), " & "48 (BC_0, BPCLK, bidir, X, 49, 0, Z), " & "47 (BC_1, *, controlr, 0), " & "46 (BC_0, A12, bidir, X, 47, 0, Z), " & "45 (BC_1, *, controlr, 0), " & "44 (BC_0, RMSYNC2, bidir, X, 45, 0, Z), " & "43 (BC_1, *, controlr, 0), " & "42 (BC_0, RSYNC2, bidir, X, 43, 0, Z), " & "41 (BC_1, *, controlr, 0), " & "40 (BC_0, TSIG2, bidir, X, 41, 0, Z), " & "39 (BC_1, *, controlr, 0), " & "38 (BC_0, TSYNC2, bidir, X, 39, 0, Z), " & "37 (BC_1, *, controlr, 0), " & "36 (BC_0, TSER2, bidir, X, 37, 0, Z), " & "35 (BC_1, *, controlr, 0), " & "34 (BC_0, TCLK2, bidir, X, 35, 0, Z), " & "33 (BC_1, *, controlr, 0), " & "32 (BC_0, RSER2, bidir, X, 33, 0, Z), " & "31 (BC_1, *, controlr, 0), " & "30 (BC_0, TSYSCLK2, bidir, X, 31, 0, PULL0)," & "29 (BC_1, *, controlr, 0), " & "28 (BC_0, RSYSCLK2, bidir, X, 29, 0, PULL0)," & "27 (BC_1, *, controlr, 0), " & "26 (BC_0, TCLK1, bidir, X, 27, 0, Z), " & "25 (BC_1, *, controlr, 0), " & "24 (BC_0, TSER1, bidir, X, 25, 0, Z), " & "23 (BC_1, *, controlr, 0), " & "22 (BC_0, TSIG1, bidir, X, 23, 0, Z), " & "21 (BC_1, *, controlr, 0), " & "20 (BC_0, RSYNC1, bidir, X, 21, 0, Z), " & "19 (BC_1, *, controlr, 0), " & "18 (BC_0, RMSYNC1, bidir, X, 19, 0, Z), " & "17 (BC_1, *, controlr, 0), " & "16 (BC_0, RSER1, bidir, X, 17, 0, Z), " & "15 (BC_1, *, controlr, 0), " & "14 (BC_0, SPI_SEL, bidir, X, 15, 0, PULL0)," & "13 (BC_1, *, controlr, 0), " & "12 (BC_0, CLKO, bidir, X, 13, 0, Z), " & "11 (BC_1, *, controlr, 0), " & "10 (BC_0, RSIG1, bidir, X, 11, 0, Z), " & "9 (BC_1, *, controlr, 0), " & "8 (BC_0, RCHBLK1, bidir, X, 9, 0, Z), " & "7 (BC_1, *, controlr, 0), " & "6 (BC_0, RCLK4, bidir, X, 7, 0, Z), " & "5 (BC_1, *, controlr, 0), " & "4 (BC_0, RCLK1, bidir, X, 5, 0, Z), " & "3 (BC_1, *, controlr, 0), " & "2 (BC_0, RCLK3, bidir, X, 3, 0, Z), " & "1 (BC_1, *, controlr, 0), " & "0 (BC_0, RCLK2, bidir, X, 1, 0, Z) "; end ds26514;