-- File Name :DS26401.BSD -- Created by :Dallas Semiconductor (Synopsys Version 2000.11 (Nov 27, 2000)) -- Documentation :DS26401 data sheets -- -- -- -- BSDL Revision :1.0 -- -- Date created :11/27/2000 -- Date modified :01/16/2003 -- Device :DS26401 -- Package :256-pin BGA -- -- IMPORTANT NOTICE -- Dallas Semiconductor customers are advised to obtain the latest version of -- device specifications before relying on any published information contained -- herein. Dallas Semiconductor assumes no responsibility or liability arising -- out of the application of any information described herein. -- -- -- -- IMPORTANT NOTICE ABOUT THE REVISION -- -- Dallas Semiconductor customers are advised to check the revision of the -- device they will be using. All the codes for the device revisions are -- herein this BSDL file. -- -- The characters "/", "(", ")" and "*" have been removed from signal names for -- compatibility with BSDL file format. -- -- entity ds26401_top is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "CSBGA_256PORT"); -- This section declares all the ports in the design. port ( bts : in bit; gclk_in : in bit; jtclk : in bit; jtdi : in bit; jtms : in bit; jtrst_n : in bit; port_csb : in bit; port_rdb : in bit; port_wr : in bit; ref_clk : in bit; reset_b : in bit; scan_en : in bit; scan_mode : in bit; test : in bit; port_addr : in bit_vector (0 to 11); rclk : in bit_vector (1 to 8); rneg : in bit_vector (1 to 8); rpos : in bit_vector (1 to 8); rsysclk_a : in bit_vector (1 to 8); tclk : in bit_vector (1 to 8); tser_a : in bit_vector (1 to 8); tsig_a : in bit_vector (1 to 8); tssync_a : in bit_vector (1 to 8); tsysclk_a : in bit_vector (1 to 8); port_data : inout bit_vector (0 to 7); rsync : inout bit_vector (1 to 8); tsync : inout bit_vector (1 to 8); bpclk : out bit; gclk_out : out bit; int_b : out bit; jtdo : out bit; rchblk_clk : out bit_vector (1 to 8); rf_rmsync : out bit_vector (1 to 8); rlof_lotc : out bit_vector (1 to 8); rlos_rsigf : out bit_vector (1 to 8); rser_a : out bit_vector (1 to 8); rsig_a : out bit_vector (1 to 8); tchblk_clk : out bit_vector (1 to 8); tclko : out bit_vector (1 to 8); tneg : out bit_vector (1 to 8); tpos : out bit_vector (1 to 8); VDD : linkage bit_vector (1 to 16); VSS : linkage bit_vector (1 to 20) ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of ds26401_top: entity is "STD_1149_1_1993" ; attribute PIN_MAP of ds26401_top: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information -- is extracted from the port-to-pin map file that was read in using -- the "read_pin_map" command. constant CSBGA_256PORT: PIN_MAP_STRING := "bts : B2," & "gclk_in : G16," & "jtclk : N10," & "jtdi : T11," & "jtms : T10," & "jtrst_n : R11," & "port_csb : B4," & "port_rdb : E7," & "port_wr : C5," & "ref_clk : F15," & "reset_b : T12," & "scan_en : P12," & "scan_mode : M10," & "test : R12," & "port_addr : (B5, A5, C6, E8, A6, B6, D7, C7, A7, D8, C8, A8)," & "rclk : (C2, H4, L4, N6, M11, L14, E16, C12)," & "rneg : (C1, H5, M4, R6, N12, L16, D16, B12)," & "rpos : (D4, J2, P1, T6, T14, L13, G12, E11)," & "rsysclk_a : (C3, H2, N2, M6, R13, L12, H12, D12)," & "tclk : (F4, L1, T3, R9, P15, J13, B15, B10)," & "tser_a : (G4, M1, N5, P9, N14, H16, B14, C9)," & "tsig_a : (G3, M2, T4, R10, M13, H14, C14, A9)," & "tssync_a : (E1, K4, T2, T8, R16, J14, D14, D10)," & "tsysclk_a : (E2, K3, P3, R8, M12, K15, B16, E10)," & "port_data : (A1, C4, A2, B3, D5, A3, D6, A4)," & "rsync : (E3, K1, M5, R7, R15, K16, E13, B11)," & "tsync : (G2, K5, R4, N9, N16, G15, A14, D9)," & "bpclk : F16," & "gclk_out : G13," & "int_b : E9," & "jtdo : P11," & "rchblk_clk : (B1, H1, L5, P6, N11, M15, E15, A13)," & "rf_rmsync : (E5, H3, N1, T5, T13, M16, F14, C13)," & "rlof_lotc : (D1, K2, T1, P7, P13, K14, C15, D11)," & "rlos_rsigf : (F5, J4, R2, T7, T16, K13, C16, A11)," & "rser_a : (E4, J1, R1, M7, R14, L15, F12, A12)," & "rsig_a : (D3, J3, N3, N7, T15, K12, F13, C11)," & "tchblk_clk : (F3, L2, R3, N8, P14, J15, A16, C10)," & "tclko : (G1, M3, P5, P10, M14, H13, D13, B8)," & "tneg : (G5, L3, P4, T9, P16, H15, A15, B9)," & "tpos : (F1, J5, N4, M8, N13, J12, E12, A10)," & "VDD : (F8, F9, G8, G9, H10, H11, H6, H7, J10, J11, J6, J7" & ", K8, K9, L8, L9)," & "VSS : (F10, F11, F6, F7, G10, G11, G6, G7, H8, H9, J8, J9" & ", K10, K11, K6, K7, L10, L11, L6, L7)"; -- This section specifies the TAP ports. -- For the TAP TCK port, the parameters in the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of jtclk : signal is (10.0e6, BOTH); attribute TAP_SCAN_IN of jtdi : signal is true; attribute TAP_SCAN_MODE of jtms : signal is true; attribute TAP_SCAN_OUT of jtdo : signal is true; attribute TAP_SCAN_RESET of jtrst_n: signal is true; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of ds26401_top: entity is 3; -- Specifies the boundary-scan instructions implemented in the -- design and their opcodes. attribute INSTRUCTION_OPCODE of ds26401_top: entity is "BYPASS (111)," & "EXTEST (000)," & "SAMPLE (010)," & "CLAMP (011)," & "HIGHZ (100)," & "USER1 (101)," & "USER2 (110)," & "IDCODE (001)"; -- Specifies the bit pattern that is loaded into the instruction -- register when the TAP controller passes through the Capture-IR -- state. The standard mandates that the two LSBs must be "01". -- The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of ds26401_top: entity is "001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID -- register during the IDCODE instruction when the TAP controller -- passes through the Capture-DR state. attribute IDCODE_REGISTER of ds26401_top: entity is "0000" & -- 4-bit version number "0000000000100101" & -- 16-bit part number "00010100001" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 -- This section specifies the test data register placed between TDI -- and TDO for each implemented instruction. attribute REGISTER_ACCESS of ds26401_top: entity is "BYPASS (BYPASS, CLAMP, HIGHZ, USER1, USER2)," & "BOUNDARY (EXTEST, SAMPLE)," & "DEVICE_ID (IDCODE)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of ds26401_top: entity is 260; -- The following list specifies the characteristics of each cell -- in the boundary scan register from TDI to TDO. -- The following is a description of the label fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not -- have a port name. -- function: Is the function of the cell as defined by the -- standard. Is one of input, output2, output3, -- bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be -- loaded with for safe operation when the software -- might otherwise choose a random value. -- ccell : The control cell number. Specifies the control -- cell that drives the output enable for this port. -- disval : Specifies the value that is loaded into the -- control cell to disable the output enable for -- the corresponding port. -- rslt : Resulting state. Shows the state of the driver -- when it is disabled. attribute BOUNDARY_REGISTER of ds26401_top: entity is -- -- num cell port function safe [ccell disval rslt] -- "259 (BC_4, tsysclk_a(5), observe_only, X), " & "258 (BC_4, tssync_a(5), observe_only, X), " & "257 (BC_2, tchblk_clk(5), output3, X, 12, 1, Z), " & "256 (BC_4, tclk(5), observe_only, X), " & "255 (BC_2, tpos(5), output3, X, 12, 1, Z), " & "254 (BC_2, tneg(5), output3, X, 12, 1, Z), " & "253 (BC_4, tser_a(5), observe_only, X), " & "252 (BC_4, tsig_a(5), observe_only, X), " & "251 (BC_4, tsync(5), observe_only, X), " & "250 (BC_2, tsync(5), output3, X, 249, 1, Z), " & "249 (BC_2, *, controlr, 1), " & "248 (BC_2, tclko(5), output3, X, 12, 1, Z), " & "247 (BC_4, rsysclk_a(6), observe_only, X), " & "246 (BC_2, rf_rmsync(6), output3, X, 245, 1, Z), " & "245 (BC_2, *, controlr, 1), " & "244 (BC_2, rchblk_clk(6), output3, X, 245, 1, Z), " & "243 (BC_4, rclk(6), observe_only, X), " & "242 (BC_4, rpos(6), observe_only, X), " & "241 (BC_4, rneg(6), observe_only, X), " & "240 (BC_2, rser_a(6), output3, X, 239, 1, Z), " & "239 (BC_2, *, controlr, 1), " & "238 (BC_2, rsig_a(6), output3, X, 239, 1, Z), " & "237 (BC_2, rlof_lotc(6), output3, X, 245, 1, Z), " & "236 (BC_2, rlos_rsigf(6), output3, X, 245, 1, Z), " & "235 (BC_4, rsync(6), observe_only, X), " & "234 (BC_2, rsync(6), output3, X, 233, 1, Z), " & "233 (BC_2, *, controlr, 1), " & "232 (BC_4, tsysclk_a(6), observe_only, X), " & "231 (BC_4, tssync_a(6), observe_only, X), " & "230 (BC_2, tchblk_clk(6), output3, X, 245, 1, Z), " & "229 (BC_4, tclk(6), observe_only, X), " & "228 (BC_2, tpos(6), output3, X, 245, 1, Z), " & "227 (BC_2, tneg(6), output3, X, 245, 1, Z), " & "226 (BC_4, tser_a(6), observe_only, X), " & "225 (BC_4, tsig_a(6), observe_only, X), " & "224 (BC_4, tsync(6), observe_only, X), " & "223 (BC_2, tsync(6), output3, X, 222, 1, Z), " & "222 (BC_2, *, controlr, 1), " & "221 (BC_2, tclko(6), output3, X, 245, 1, Z), " & "220 (BC_4, gclk_in, observe_only, X), " & "219 (BC_2, gclk_out, output3, X, 245, 1, Z), " & "218 (BC_4, ref_clk, observe_only, X), " & "217 (BC_2, bpclk, output3, X, 245, 1, Z), " & "216 (BC_4, rsysclk_a(7), observe_only, X), " & "215 (BC_2, rf_rmsync(7), output3, X, 214, 1, Z), " & "214 (BC_2, *, controlr, 1), " & "213 (BC_2, rchblk_clk(7), output3, X, 214, 1, Z), " & "212 (BC_4, rclk(7), observe_only, X), " & "211 (BC_4, rpos(7), observe_only, X), " & "210 (BC_4, rneg(7), observe_only, X), " & "209 (BC_2, rser_a(7), output3, X, 208, 1, Z), " & "208 (BC_2, *, controlr, 1), " & "207 (BC_2, rsig_a(7), output3, X, 208, 1, Z), " & "206 (BC_2, rlof_lotc(7), output3, X, 214, 1, Z), " & "205 (BC_2, rlos_rsigf(7), output3, X, 214, 1, Z), " & "204 (BC_4, rsync(7), observe_only, X), " & "203 (BC_2, rsync(7), output3, X, 202, 1, Z), " & "202 (BC_2, *, controlr, 1), " & "201 (BC_4, tsysclk_a(7), observe_only, X), " & "200 (BC_4, tssync_a(7), observe_only, X), " & "199 (BC_2, tchblk_clk(7), output3, X, 214, 1, Z), " & "198 (BC_4, tclk(7), observe_only, X), " & "197 (BC_2, tpos(7), output3, X, 214, 1, Z), " & "196 (BC_2, tneg(7), output3, X, 214, 1, Z), " & "195 (BC_4, tser_a(7), observe_only, X), " & "194 (BC_4, tsig_a(7), observe_only, X), " & "193 (BC_4, tsync(7), observe_only, X), " & "192 (BC_2, tsync(7), output3, X, 191, 1, Z), " & "191 (BC_2, *, controlr, 1), " & "190 (BC_2, tclko(7), output3, X, 214, 1, Z), " & "189 (BC_4, rsysclk_a(8), observe_only, X), " & "188 (BC_2, rf_rmsync(8), output3, X, 187, 1, Z), " & "187 (BC_2, *, controlr, 1), " & "186 (BC_2, rchblk_clk(8), output3, X, 187, 1, Z), " & "185 (BC_4, rclk(8), observe_only, X), " & "184 (BC_4, rpos(8), observe_only, X), " & "183 (BC_4, rneg(8), observe_only, X), " & "182 (BC_2, rser_a(8), output3, X, 181, 1, Z), " & "181 (BC_2, *, controlr, 1), " & "180 (BC_2, rsig_a(8), output3, X, 181, 1, Z), " & "179 (BC_2, rlof_lotc(8), output3, X, 187, 1, Z), " & "178 (BC_2, rlos_rsigf(8), output3, X, 187, 1, Z), " & "177 (BC_4, rsync(8), observe_only, X), " & "176 (BC_2, rsync(8), output3, X, 175, 1, Z), " & "175 (BC_2, *, controlr, 1), " & "174 (BC_4, tsysclk_a(8), observe_only, X), " & "173 (BC_4, tssync_a(8), observe_only, X), " & "172 (BC_2, tchblk_clk(8), output3, X, 187, 1, Z), " & "171 (BC_4, tclk(8), observe_only, X), " & "170 (BC_2, tpos(8), output3, X, 187, 1, Z), " & "169 (BC_2, tneg(8), output3, X, 187, 1, Z), " & "168 (BC_4, tser_a(8), observe_only, X), " & "167 (BC_4, tsig_a(8), observe_only, X), " & "166 (BC_4, tsync(8), observe_only, X), " & "165 (BC_2, tsync(8), output3, X, 164, 1, Z), " & "164 (BC_2, *, controlr, 1), " & "163 (BC_2, tclko(8), output3, X, 187, 1, Z), " & "162 (BC_0, *, internal, 0), " & "161 (BC_0, *, internal, 0), " & "160 (BC_2, int_b, output2, 1, 160, 1, weak1), " & "159 (BC_4, port_addr(11), observe_only, X), " & "158 (BC_4, port_addr(10), observe_only, X), " & "157 (BC_4, port_addr(9), observe_only, X), " & "156 (BC_4, port_addr(8), observe_only, X), " & "155 (BC_4, port_addr(7), observe_only, X), " & "154 (BC_4, port_addr(6), observe_only, X), " & "153 (BC_4, port_addr(5), observe_only, X), " & "152 (BC_4, port_addr(4), observe_only, X), " & "151 (BC_4, port_addr(3), observe_only, X), " & "150 (BC_4, port_addr(2), observe_only, X), " & "149 (BC_4, port_addr(1), observe_only, X), " & "148 (BC_4, port_addr(0), observe_only, X), " & "147 (BC_4, port_rdb, observe_only, X), " & "146 (BC_4, port_wr, observe_only, X), " & "145 (BC_4, port_csb, observe_only, X), " & "144 (BC_4, port_data(7), observe_only, X), " & "143 (BC_2, port_data(7), output3, X, 142, 1, Z), " & "142 (BC_2, *, controlr, 1), " & "141 (BC_4, port_data(6), observe_only, X), " & "140 (BC_2, port_data(6), output3, X, 142, 1, Z), " & "139 (BC_4, port_data(5), observe_only, X), " & "138 (BC_2, port_data(5), output3, X, 142, 1, Z), " & "137 (BC_4, port_data(4), observe_only, X), " & "136 (BC_2, port_data(4), output3, X, 142, 1, Z), " & "135 (BC_4, port_data(3), observe_only, X), " & "134 (BC_2, port_data(3), output3, X, 142, 1, Z), " & "133 (BC_4, port_data(2), observe_only, X), " & "132 (BC_2, port_data(2), output3, X, 142, 1, Z), " & "131 (BC_4, port_data(1), observe_only, X), " & "130 (BC_2, port_data(1), output3, X, 142, 1, Z), " & "129 (BC_4, port_data(0), observe_only, X), " & "128 (BC_2, port_data(0), output3, X, 142, 1, Z), " & "127 (BC_4, bts, observe_only, X), " & "126 (BC_4, rsysclk_a(1), observe_only, X), " & "125 (BC_2, rf_rmsync(1), output3, X, 124, 1, Z), " & "124 (BC_2, *, controlr, 1), " & "123 (BC_2, rchblk_clk(1), output3, X, 124, 1, Z), " & "122 (BC_4, rclk(1), observe_only, X), " & "121 (BC_4, rpos(1), observe_only, X), " & "120 (BC_4, rneg(1), observe_only, X), " & "119 (BC_2, rser_a(1), output3, X, 118, 1, Z), " & "118 (BC_2, *, controlr, 1), " & "117 (BC_2, rsig_a(1), output3, X, 118, 1, Z), " & "116 (BC_2, rlof_lotc(1), output3, X, 124, 1, Z), " & "115 (BC_2, rlos_rsigf(1), output3, X, 124, 1, Z), " & "114 (BC_4, rsync(1), observe_only, X), " & "113 (BC_2, rsync(1), output3, X, 112, 1, Z), " & "112 (BC_2, *, controlr, 1), " & "111 (BC_4, tsysclk_a(1), observe_only, X), " & "110 (BC_4, tssync_a(1), observe_only, X), " & "109 (BC_2, tchblk_clk(1), output3, X, 124, 1, Z), " & "108 (BC_4, tclk(1), observe_only, X), " & "107 (BC_2, tpos(1), output3, X, 124, 1, Z), " & "106 (BC_2, tneg(1), output3, X, 124, 1, Z), " & "105 (BC_4, tser_a(1), observe_only, X), " & "104 (BC_4, tsig_a(1), observe_only, X), " & "103 (BC_4, tsync(1), observe_only, X), " & "102 (BC_2, tsync(1), output3, X, 101, 1, Z), " & "101 (BC_2, *, controlr, 1), " & "100 (BC_2, tclko(1), output3, X, 124, 1, Z), " & "99 (BC_4, rsysclk_a(2), observe_only, X), " & "98 (BC_2, rf_rmsync(2), output3, X, 97, 1, Z), " & "97 (BC_2, *, controlr, 1), " & "96 (BC_2, rchblk_clk(2), output3, X, 97, 1, Z), " & "95 (BC_4, rclk(2), observe_only, X), " & "94 (BC_4, rpos(2), observe_only, X), " & "93 (BC_4, rneg(2), observe_only, X), " & "92 (BC_2, rser_a(2), output3, X, 91, 1, Z), " & "91 (BC_2, *, controlr, 1), " & "90 (BC_2, rsig_a(2), output3, X, 91, 1, Z), " & "89 (BC_2, rlof_lotc(2), output3, X, 97, 1, Z), " & "88 (BC_2, rlos_rsigf(2), output3, X, 97, 1, Z), " & "87 (BC_4, rsync(2), observe_only, X), " & "86 (BC_2, rsync(2), output3, X, 85, 1, Z), " & "85 (BC_2, *, controlr, 1), " & "84 (BC_4, tsysclk_a(2), observe_only, X), " & "83 (BC_4, tssync_a(2), observe_only, X), " & "82 (BC_2, tchblk_clk(2), output3, X, 97, 1, Z), " & "81 (BC_4, tclk(2), observe_only, X), " & "80 (BC_2, tpos(2), output3, X, 97, 1, Z), " & "79 (BC_2, tneg(2), output3, X, 97, 1, Z), " & "78 (BC_4, tser_a(2), observe_only, X), " & "77 (BC_4, tsig_a(2), observe_only, X), " & "76 (BC_4, tsync(2), observe_only, X), " & "75 (BC_2, tsync(2), output3, X, 74, 1, Z), " & "74 (BC_2, *, controlr, 1), " & "73 (BC_2, tclko(2), output3, X, 97, 1, Z), " & "72 (BC_4, rsysclk_a(3), observe_only, X), " & "71 (BC_2, rf_rmsync(3), output3, X, 70, 1, Z), " & "70 (BC_2, *, controlr, 1), " & "69 (BC_2, rchblk_clk(3), output3, X, 70, 1, Z), " & "68 (BC_4, rclk(3), observe_only, X), " & "67 (BC_4, rpos(3), observe_only, X), " & "66 (BC_4, rneg(3), observe_only, X), " & "65 (BC_2, rser_a(3), output3, X, 64, 1, Z), " & "64 (BC_2, *, controlr, 1), " & "63 (BC_2, rsig_a(3), output3, X, 64, 1, Z), " & "62 (BC_2, rlof_lotc(3), output3, X, 70, 1, Z), " & "61 (BC_2, rlos_rsigf(3), output3, X, 70, 1, Z), " & "60 (BC_4, rsync(3), observe_only, X), " & "59 (BC_2, rsync(3), output3, X, 58, 1, Z), " & "58 (BC_2, *, controlr, 1), " & "57 (BC_4, tsysclk_a(3), observe_only, X), " & "56 (BC_4, tssync_a(3), observe_only, X), " & "55 (BC_2, tchblk_clk(3), output3, X, 70, 1, Z), " & "54 (BC_4, tclk(3), observe_only, X), " & "53 (BC_2, tpos(3), output3, X, 70, 1, Z), " & "52 (BC_2, tneg(3), output3, X, 70, 1, Z), " & "51 (BC_4, tser_a(3), observe_only, X), " & "50 (BC_4, tsig_a(3), observe_only, X), " & "49 (BC_4, tsync(3), observe_only, X), " & "48 (BC_2, tsync(3), output3, X, 47, 1, Z), " & "47 (BC_2, *, controlr, 1), " & "46 (BC_2, tclko(3), output3, X, 70, 1, Z), " & "45 (BC_4, rsysclk_a(4), observe_only, X), " & "44 (BC_2, rf_rmsync(4), output3, X, 43, 1, Z), " & "43 (BC_2, *, controlr, 1), " & "42 (BC_2, rchblk_clk(4), output3, X, 43, 1, Z), " & "41 (BC_4, rclk(4), observe_only, X), " & "40 (BC_4, rpos(4), observe_only, X), " & "39 (BC_4, rneg(4), observe_only, X), " & "38 (BC_2, rser_a(4), output3, X, 37, 1, Z), " & "37 (BC_2, *, controlr, 1), " & "36 (BC_2, rsig_a(4), output3, X, 37, 1, Z), " & "35 (BC_2, rlof_lotc(4), output3, X, 43, 1, Z), " & "34 (BC_2, rlos_rsigf(4), output3, X, 43, 1, Z), " & "33 (BC_4, rsync(4), observe_only, X), " & "32 (BC_2, rsync(4), output3, X, 31, 1, Z), " & "31 (BC_2, *, controlr, 1), " & "30 (BC_4, tsysclk_a(4), observe_only, X), " & "29 (BC_4, tssync_a(4), observe_only, X), " & "28 (BC_2, tchblk_clk(4), output3, X, 43, 1, Z), " & "27 (BC_4, tclk(4), observe_only, X), " & "26 (BC_2, tpos(4), output3, X, 43, 1, Z), " & "25 (BC_2, tneg(4), output3, X, 43, 1, Z), " & "24 (BC_4, tser_a(4), observe_only, X), " & "23 (BC_4, tsig_a(4), observe_only, X), " & "22 (BC_4, tsync(4), observe_only, X), " & "21 (BC_2, tsync(4), output3, X, 20, 1, Z), " & "20 (BC_2, *, controlr, 1), " & "19 (BC_2, tclko(4), output3, X, 43, 1, Z), " & "18 (BC_4, reset_b, observe_only, X), " & "17 (BC_4, test, observe_only, X), " & "16 (BC_4, scan_mode, observe_only, X), " & "15 (BC_4, scan_en, observe_only, X), " & "14 (BC_4, rsysclk_a(5), observe_only, X), " & "13 (BC_2, rf_rmsync(5), output3, X, 12, 1, Z), " & "12 (BC_2, *, controlr, 1), " & "11 (BC_2, rchblk_clk(5), output3, X, 12, 1, Z), " & "10 (BC_4, rclk(5), observe_only, X), " & "9 (BC_4, rpos(5), observe_only, X), " & "8 (BC_4, rneg(5), observe_only, X), " & "7 (BC_2, rser_a(5), output3, X, 6, 1, Z), " & "6 (BC_2, *, controlr, 1), " & "5 (BC_2, rsig_a(5), output3, X, 6, 1, Z), " & "4 (BC_2, rlof_lotc(5), output3, X, 12, 1, Z), " & "3 (BC_2, rlos_rsigf(5), output3, X, 12, 1, Z), " & "2 (BC_4, rsync(5), observe_only, X), " & "1 (BC_2, rsync(5), output3, X, 0, 1, Z), " & "0 (BC_2, *, controlr, 1) "; end ds26401_top;