-- File Name :DS21458CSBGA.BSD -- Created by :Dallas Semiconductor -- Documentation :DS21458 series data sheets -- -- -- -- BSDL Revision :1.1 -- -- Date created :02/19/2004 -- Date modified :02/19/2004 -- Device :DS21458CSBGA -- Package :256-pin CSBGA -- -- IMPORTANT NOTICE -- -- Dallas Semiconductor customers are advised to obtain the latest version of -- device specifications before relying on any published information contained -- herein. Dallas Semiconductor assumes no responsibility or liability arising -- out of the application of any information described herein. -- -- -- IMPORTANT NOTICE ABOUT THE REVISION -- -- Dallas Semiconductor customers are advised to check the revision of the -- device they will be using. All the codes for the device revisions are -- herein this BSDL file. -- -- The characters "/", "(", ")" and "*" have been removed from signal names for -- compatibility with BSDL file format. -- -- entity DS21458CSBGA is generic (PHYSICAL_PIN_MAP : string := "CSBGA_256"); port ( A0 : in bit; A1 : in bit; A2 : in bit; A3 : in bit; A4 : in bit; A5 : in bit; A6 : in bit; A7_ALE_AS : in bit; A8 : in bit; A9 : in bit; BPCLK1 : buffer bit ; BPCLK2 : buffer bit ; BPCLK3 : buffer bit ; BPCLK4 : buffer bit ; BTS : in bit; CS : in bit; D0_AD0 : inout bit; D1_AD1 : inout bit; D2_AD2 : inout bit; D3_AD3 : inout bit; D4_AD4 : inout bit; D5_AD5 : inout bit; D6_AD6 : inout bit; D7_AD7 : inout bit; ESIBRD : inout bit; ESIBS0 : inout bit; ESIBS1 : inout bit; INT : out bit; JTCLK : in bit; JTDI : in bit; JTDO : out bit ; JTMS : in bit; JTRST : in bit; MUX : in bit; RCHBLK1 : buffer bit; RCHBLK2 : buffer bit; RCHBLK3 : buffer bit; RCHBLK4 : buffer bit; RCHCLK1 : buffer bit; RCHCLK2 : buffer bit; RCHCLK3 : buffer bit; RCHCLK4 : buffer bit; RCLK1 : buffer bit; RCLK2 : buffer bit; RCLK3 : buffer bit; RCLK4 : buffer bit; RCLKO1 : buffer bit; RCLKO2 : buffer bit; RCLKO3 : buffer bit; RCLKO4 : buffer bit; RD_DS : in bit; RFSYNC1 : buffer bit; RFSYNC2 : buffer bit; RFSYNC3 : buffer bit; RFSYNC4 : buffer bit; RLCLK1 : buffer bit; RLCLK2 : buffer bit; RLCLK3 : buffer bit; RLCLK4 : buffer bit; RLINK1 : buffer bit; RLINK2 : buffer bit; RLINK3 : buffer bit; RLINK4 : buffer bit; RLOS_LOTC1 : buffer bit; RLOS_LOTC2 : buffer bit; RLOS_LOTC3 : buffer bit; RLOS_LOTC4 : buffer bit; RMSYNC1 : buffer bit; RMSYNC2 : buffer bit; RMSYNC3 : buffer bit; RMSYNC4 : buffer bit; RNEGO1 : buffer bit; RNEGO2 : buffer bit; RNEGO3 : buffer bit; RNEGO4 : buffer bit; RPOSO1 : buffer bit; RPOSO2 : buffer bit; RPOSO3 : buffer bit; RPOSO4 : buffer bit; RSER1 : buffer bit; RSER2 : buffer bit; RSER3 : buffer bit; RSER4 : buffer bit; RSIG1 : buffer bit; RSIG2 : buffer bit; RSIG3 : buffer bit; RSIG4 : buffer bit; RSIGF1 : buffer bit; RSIGF2 : buffer bit; RSIGF3 : buffer bit; RSIGF4 : buffer bit; RSYNC1 : inout bit; RSYNC2 : inout bit; RSYNC3 : inout bit; RSYNC4 : inout bit; RSYSCLK1 : in bit; RSYSCLK2 : in bit; RSYSCLK3 : in bit; RSYSCLK4 : in bit; TCHBLK1 : buffer bit; TCHBLK2 : buffer bit; TCHBLK3 : buffer bit; TCHBLK4 : buffer bit; TCHCLK1 : buffer bit; TCHCLK2 : buffer bit; TCHCLK3 : buffer bit; TCHCLK4 : buffer bit; TCLK1 : in bit; TCLK2 : in bit; TCLK3 : in bit; TCLK4 : in bit; TCLKO1 : buffer bit; TCLKO2 : buffer bit; TCLKO3 : buffer bit; TCLKO4 : buffer bit; TLCLK1 : buffer bit; TLCLK2 : buffer bit; TLCLK3 : buffer bit; TLCLK4 : buffer bit; TLINK1 : in bit; TLINK2 : in bit; TLINK3 : in bit; TLINK4 : in bit; TNEGO1 : buffer bit; TNEGO2 : buffer bit; TNEGO3 : buffer bit; TNEGO4 : buffer bit; TPOSO1 : buffer bit; TPOSO2 : buffer bit; TPOSO3 : buffer bit; TPOSO4 : buffer bit; TSER1 : in bit; TSER2 : in bit; TSER3 : in bit; TSER4 : in bit; TSIG1 : in bit; TSIG2 : in bit; TSIG3 : in bit; TSIG4 : in bit; TSSYNC1 : in bit; TSSYNC2 : in bit; TSSYNC3 : in bit; TSSYNC4 : in bit; TSTRST : in bit; TSYNC1 : inout bit; TSYNC2 : inout bit; TSYNC3 : inout bit; TSYNC4 : inout bit; TSYSCLK1 : in bit; TSYSCLK2 : in bit; TSYSCLK3 : in bit; TSYSCLK4 : in bit; WR_R_W : in bit; RVDD :linkage bit_vector(1 to 4); RVSS :linkage bit_vector(1 to 12); TVDD :linkage bit_vector(1 to 8); TVSS :linkage bit_vector(1 to 8); VDD :linkage bit_vector(1 to 12); VSS :linkage bit_vector(1 to 12); NoConnect :linkage bit_vector(1 to 20) ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of DS21458CSBGA : entity is "STD_1149_1_1993"; attribute PIN_MAP of DS21458CSBGA : entity is PHYSICAL_PIN_MAP; constant CSBGA_256 : PIN_MAP_STRING := "A0 : H2 ,"& "A1 : E10 ,"& "A2 : H3 ,"& "A3 : G4 ,"& "A4 : N7 ,"& "A5 : B9 ,"& "A6 : T7 ,"& "A7_ALE_AS : G2 ,"& "A8 : H6 ,"& "A9 : J11 ,"& "BPCLK1 : J5 ,"& "BPCLK2 : H13 ,"& "BPCLK3 : E8 ,"& "BPCLK4 : N9 ,"& "BTS : B10 ,"& "CS : M8 ,"& "D0_AD0 : P8 ,"& "D1_AD1 : D10 ,"& "D2_AD2 : N8 ,"& "D3_AD3 : P7 ,"& "D4_AD4 : M7 ,"& "D5_AD5 : R7 ,"& "D6_AD6 : G1 ,"& "D7_AD7 : G3 ,"& "ESIBRD : H8 ,"& "ESIBS0 : J8 ,"& "ESIBS1 : J9 ,"& "INT : H5 ,"& "JTCLK : K16 ,"& "JTDI : C10 ,"& "JTDO : K13 ,"& "JTMS : J15 ,"& "JTRST : K14 ,"& "MUX : R8 ,"& "RCHBLK1 : K3 ,"& "RCHBLK2 : G10 ,"& "RCHBLK3 : C7 ,"& "RCHBLK4 : R11 ,"& "RCHCLK1 : L2 ,"& "RCHCLK2 : G11 ,"& "RCHCLK3 : D7 ,"& "RCHCLK4 : M9 ,"& "RCLK1 : K8 ,"& "RCLK2 : F10 ,"& "RCLK3 : G5 ,"& "RCLK4 : K12 ,"& "RCLKO1 : R1 ,"& "RCLKO2 : C14 ,"& "RCLKO3 : A2 ,"& "RCLKO4 : P14 ,"& "RD_DS : A10 ,"& "RFSYNC1 : K4 ,"& "RFSYNC2 : G14 ,"& "RFSYNC3 : C6 ,"& "RFSYNC4 : P11 ,"& "RLCLK1 : M2 ,"& "RLCLK2 : F15 ,"& "RLCLK3 : B6 ,"& "RLCLK4 : R12 ,"& "RLINK1 : P2 ,"& "RLINK2 : C15 ,"& "RLINK3 : C3 ,"& "RLINK4 : T15 ,"& "RLOS_LOTC1 : K5 ,"& "RLOS_LOTC2 : E15 ,"& "RLOS_LOTC3 : D6 ,"& "RLOS_LOTC4 : P12 ,"& "RMSYNC1 : M3 ,"& "RMSYNC2 : G13 ,"& "RMSYNC3 : E6 ,"& "RMSYNC4 : M10 ,"& "RNEGO1 : J2 ,"& "RNEGO2 : H11 ,"& "RNEGO3 : F8 ,"& "RNEGO4 : P10 ,"& "RPOSO1 : J6 ,"& "RPOSO2 : H12 ,"& "RPOSO3 : F9 ,"& "RPOSO4 : N10 ,"& "RSER1 : J4 ,"& "RSER2 : H14 ,"& "RSER3 : C8 ,"& "RSER4 : P9 ,"& "RSIG1 : K2 ,"& "RSIG2 : G15 ,"& "RSIG3 : B7 ,"& "RSIG4 : R10 ,"& "RSIGF1 : L3 ,"& "RSIGF2 : F14 ,"& "RSIGF3 : E7 ,"& "RSIGF4 : N11 ,"& "RSYNC1 : K6 ,"& "RSYNC2 : E14 ,"& "RSYNC3 : B5 ,"& "RSYNC4 : N12 ,"& "RSYSCLK1 : J3 ,"& "RSYSCLK2 : H15 ,"& "RSYSCLK3 : B8 ,"& "RSYSCLK4 : R9 ,"& "TCHBLK1 : N2 ,"& "TCHBLK2 : E13 ,"& "TCHBLK3 : C5 ,"& "TCHBLK4 : R13 ,"& "TCHCLK1 : J7 ,"& "TCHCLK2 : D15 ,"& "TCHCLK3 : B4 ,"& "TCHCLK4 : P13 ,"& "TCLK1 : L5 ,"& "TCLK2 : G12 ,"& "TCLK3 : F6 ,"& "TCLK4 : L9 ,"& "TCLKO1 : T2 ,"& "TCLKO2 : A15 ,"& "TCLKO3 : B2 ,"& "TCLKO4 : R16 ,"& "TLCLK1 : P1 ,"& "TLCLK2 : C16 ,"& "TLCLK3 : C4 ,"& "TLCLK4 : T14 ,"& "TLINK1 : K7 ,"& "TLINK2 : F11 ,"& "TLINK3 : G7 ,"& "TLINK4 : L12 ,"& "TNEGO1 : T1 ,"& "TNEGO2 : B15 ,"& "TNEGO3 : A1 ,"& "TNEGO4 : T16 ,"& "TPOSO1 : R2 ,"& "TPOSO2 : A16 ,"& "TPOSO3 : B1 ,"& "TPOSO4 : R15 ,"& "TSER1 : M6 ,"& "TSER2 : G9 ,"& "TSER3 : G6 ,"& "TSER4 : K10 ,"& "TSIG1 : L7 ,"& "TSIG2 : E11 ,"& "TSIG3 : F5 ,"& "TSIG4 : K11 ,"& "TSSYNC1 : M4 ,"& "TSSYNC2 : D14 ,"& "TSSYNC3 : A3 ,"& "TSSYNC4 : M11 ,"& "TSTRST : K15 ,"& "TSYNC1 : N3 ,"& "TSYNC2 : B16 ,"& "TSYNC3 : B3 ,"& "TSYNC4 : R14 ,"& "TSYSCLK1 : H7 ,"& "TSYSCLK2 : J10 ,"& "TSYSCLK3 : D8 ,"& "TSYSCLK4 : L8 ,"& "WR_R_W : C9 ,"& "TVDD : (R6, T6, A11, B11, F1, F2, L15, L16) ,"& "TVSS : (R5, T5, A12, B12, E1, E2, M15, M16) ,"& "RVDD : (H1, J16, A9, T8) ,"& "RVSS : (N1, J1, M1, E16, H16, D16, A5, A8, A4, T12, T13, T9) ,"& "VDD : (P4, P5, P6, C11, C12, C13, D3, E3, F3, L14, M14, N14) ,"& "VSS : (N4, N5, N6, D11, D12, D13, D4, E4, F4, L13, M13, N13) ,"& "NoConnect :(E9, K9, P3, H9, H10, G8, L6, F12, F7, L11, J14, J13, M5, E12, E5, M12, L4, F13, D5, L10)"; -- MAKE SURE THAT ALL THESE NO CONNECTS ARE ON ONE LINE. OTHERWISE -- THIS BSDL FILE WILL SHOW SOME ERROR. -- This section specifies the TAP ports. -- For the TAP TCK port, the parameters in the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_IN of JTDI :signal is true; attribute TAP_SCAN_MODE of JTMS :signal is true; attribute TAP_SCAN_OUT of JTDO :signal is true; attribute TAP_SCAN_RESET of JTRST :signal is true; attribute TAP_SCAN_CLOCK of JTCLK :signal is (10.00e6,BOTH); -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of DS21458CSBGA :entity is 3; -- Specifies the boundary-scan instructions implemented in the -- design and their opcodes. attribute INSTRUCTION_OPCODE of DS21458CSBGA :entity is "EXTEST (000),"& "BYPASS (111),"& "SAMPLE (010),"& "IDCODE (001),"& "CLAMP (011),"& -- "USER1 (101)," & -- "USER2 (110)," & "HIGHZ (100)"; -- Specifies the bit pattern that is loaded into the instruction -- register when the TAP controller passes through the Capture-IR -- state. The standard mandates that the two LSBs must be "01". -- The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of DS21458CSBGA :entity is "001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID -- register during the IDCODE instruction when the TAP controller -- passes through the Capture-DR state. -- 10022143 (HEX) attribute IDCODE_REGISTER of DS21458CSBGA :entity is "0001"& -- 4-bit Version for A2 "0000000000100010"& -- 16-bit Part Number "00010100001"& -- 11-bit Manufacturer's Identity "1"; -- Mandatory LSB -- This section specifies the test data register placed between TDI -- and TDO for each implemented instruction. -- attribute REGISTER_ACCESS of DS21448_top: entity is -- "BYPASS (BYPASS, CLAMP, HIGHZ, USER1, USER2)," & -- "BOUNDARY (EXTEST, SAMPLE)," & -- "DEVICE_ID (IDCODE)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of DS21458CSBGA :entity is 204; attribute BOUNDARY_REGISTER of DS21458CSBGA :entity is -- -- num cell port function safe [ccell disval rslt] -- " 0 (BC_1, RCLKO3 , output2 , X),"& " 1 (BC_1, RLINK3 , output2 , X),"& " 2 (BC_7, TSYNC3 , bidir , 0, 3 , 0, Z),"& " 3 (BC_2, * , control , 0),"& " 4 (BC_1, TSSYNC3 , input , X),"& " 5 (BC_1, TLCLK3 , output2 , X),"& " 6 (BC_1, TCHCLK3 , output2 , X),"& " 7 (BC_1, TCHBLK3 , output2 , X),"& " 8 (BC_7, RSYNC3 , bidir , 0, 9 , 0, Z),"& " 9 (BC_2, * , control , 0),"& " 10 (BC_1, RSIGF3 , output2 , X),"& " 11 (BC_1, RMSYNC3 , output2 , X),"& " 12 (BC_1, RLOS_LOTC3 , output2 , X),"& " 13 (BC_1, RLCLK3 , output2 , X),"& " 14 (BC_1, RFSYNC3 , output2 , X),"& " 15 (BC_1, RCHCLK3 , output2 , X),"& " 16 (BC_1, RCHBLK3 , output2 , X),"& " 17 (BC_7, ESIBS1 , bidir , 0, 18 , 0, Z),"& " 18 (BC_2, * , control , 0),"& " 19 (BC_7, ESIBS0 , bidir , 0, 20 , 0, Z),"& " 20 (BC_2, * , control , 0),"& " 21 (BC_7, ESIBRD , bidir , 0, 22 , 0, Z),"& " 22 (BC_2, * , control , 0),"& " 23 (BC_1, RSIG3 , output2 , X),"& " 24 (BC_0, * , internal , X),"& " 25 (BC_0, * , internal , X),"& " 26 (BC_1, RNEGO3 , output2 , X),"& " 27 (BC_1, RPOSO3 , output2 , X),"& " 28 (BC_1, BPCLK3 , output2 , X),"& " 29 (BC_1, RSER3 , output2 , X),"& " 30 (BC_1, RSYSCLK3 , input , X),"& " 31 (BC_1, TSYSCLK3 , input , X),"& " 32 (BC_0, * , internal , X),"& " 33 (BC_0, * , internal , X),"& " 34 (BC_1, WR_R_W , input , X),"& " 35 (BC_1, A5 , input , X),"& " 36 (BC_1, A1 , input , X),"& " 37 (BC_7, D1_AD1 , bidir , 0, 133 , 0, Z),"& " 38 (BC_1, RD_DS , input , X),"& " 39 (BC_1, BTS , input , X),"& " 40 (BC_0, * , internal , X),"& " 41 (BC_1, RCLK2 , output2 , X),"& " 42 (BC_1, TSIG2 , input , X),"& " 43 (BC_1, TSER2 , input , X),"& " 44 (BC_1, TLINK2 , input , X),"& " 45 (BC_0, * , internal , X),"& " 46 (BC_1, TCLK2 , input , X),"& " 47 (BC_0, * , internal , X),"& " 48 (BC_0, * , internal , X),"& " 49 (BC_1, TCLKO2 , output2 , X),"& " 50 (BC_1, TPOSO2 , output2 , X),"& " 51 (BC_1, TNEGO2 , output2 , X),"& " 52 (BC_1, RCLKO2 , output2 , X),"& " 53 (BC_1, RLINK2 , output2 , X),"& " 54 (BC_7, TSYNC2 , bidir , 0, 55 , 0, Z),"& " 55 (BC_2, * , control , 0),"& " 56 (BC_1, TSSYNC2 , input , X),"& " 57 (BC_1, TLCLK2 , output2 , X),"& " 58 (BC_1, TCHCLK2 , output2 , X),"& " 59 (BC_1, TCHBLK2 , output2 , X),"& " 60 (BC_7, RSYNC2 , bidir , 0, 61 , 0, Z),"& " 61 (BC_2, * , control , 0),"& " 62 (BC_1, RSIGF2 , output2 , X),"& " 63 (BC_1, RMSYNC2 , output2 , X),"& " 64 (BC_1, RLOS_LOTC2 , output2 , X),"& " 65 (BC_1, RLCLK2 , output2 , X),"& " 66 (BC_1, RFSYNC2 , output2 , X),"& " 67 (BC_1, RCHCLK2 , output2 , X),"& " 68 (BC_1, RCHBLK2 , output2 , X),"& " 69 (BC_0, * , internal , X),"& " 70 (BC_0, * , internal , 0),"& " 71 (BC_0, * , internal , X),"& " 72 (BC_0, * , internal , 0),"& " 73 (BC_0, * , internal , X),"& " 74 (BC_0, * , internal , 0),"& " 75 (BC_1, RSIG2 , output2 , X),"& " 76 (BC_0, * , internal , X),"& " 77 (BC_0, * , internal , X),"& " 78 (BC_1, RNEGO2 , output2 , X),"& " 79 (BC_1, RPOSO2 , output2 , X),"& " 80 (BC_1, BPCLK2 , output2 , X),"& " 81 (BC_1, RSER2 , output2 , X),"& " 82 (BC_1, RSYSCLK2 , input , X),"& " 83 (BC_1, TSYSCLK2 , input , X),"& " 84 (BC_1, A9 , input , X),"& " 85 (BC_1, TSTRST , input , X),"& " 86 (BC_0, * , internal , X),"& " 87 (BC_1, RCLK4 , output2 , X),"& " 88 (BC_1, TSIG4 , input , X),"& " 89 (BC_1, TSER4 , input , X),"& " 90 (BC_1, TLINK4 , input , X),"& " 91 (BC_0, * , internal , X),"& " 92 (BC_1, TCLK4 , input , X),"& " 93 (BC_0, * , internal , X),"& " 94 (BC_0, * , internal , X),"& " 95 (BC_1, TCLKO4 , output2 , X),"& " 96 (BC_1, TPOSO4 , output2 , X),"& " 97 (BC_1, TNEGO4 , output2 , X),"& " 98 (BC_1, RCLKO4 , output2 , X),"& " 99 (BC_1, RLINK4 , output2 , X),"& " 100 (BC_7, TSYNC4 , bidir , 0, 101 , 0, Z),"& " 101 (BC_2, * , control , 0),"& " 102 (BC_1, TSSYNC4 , input , X),"& " 103 (BC_1, TLCLK4 , output2 , X),"& " 104 (BC_1, TCHCLK4 , output2 , X),"& " 105 (BC_1, TCHBLK4 , output2 , X),"& " 106 (BC_7, RSYNC4 , bidir , 0, 107 , 0, Z),"& " 107 (BC_2, * , control , 0),"& " 108 (BC_1, RSIGF4 , output2 , X),"& " 109 (BC_1, RMSYNC4 , output2 , X),"& " 110 (BC_1, RLOS_LOTC4 , output2 , X),"& " 111 (BC_1, RLCLK4 , output2 , X),"& " 112 (BC_1, RFSYNC4 , output2 , X),"& " 113 (BC_1, RCHCLK4 , output2 , X),"& " 114 (BC_1, RCHBLK4 , output2 , X),"& " 115 (BC_0, * , internal , X),"& " 116 (BC_0, * , internal , 0),"& " 117 (BC_0, * , internal , X),"& " 118 (BC_0, * , internal , 0),"& " 119 (BC_0, * , internal , X),"& " 120 (BC_0, * , internal , 0),"& " 121 (BC_1, RSIG4 , output2 , X),"& " 122 (BC_0, * , internal , X),"& " 123 (BC_0, * , internal , X),"& " 124 (BC_1, RNEGO4 , output2 , X),"& " 125 (BC_1, RPOSO4 , output2 , X),"& " 126 (BC_1, BPCLK4 , output2 , X),"& " 127 (BC_1, RSER4 , output2 , X),"& " 128 (BC_1, RSYSCLK4 , input , X),"& " 129 (BC_1, TSYSCLK4 , input , X),"& " 130 (BC_1, CS , input , X),"& " 131 (BC_7, D2_AD2 , bidir , 0, 133 , 0, Z),"& " 132 (BC_7, D0_AD0 , bidir , 0, 133 , 0, Z),"& " 133 (BC_2, * , control , 0),"& " 134 (BC_1, MUX , input , X),"& " 135 (BC_7, D4_AD4 , bidir , 0, 133 , 0, Z),"& " 136 (BC_1, A4 , input , X),"& " 137 (BC_1, A6 , input , X),"& " 138 (BC_7, D3_AD3 , bidir , 0, 133 , 0, Z),"& " 139 (BC_7, D5_AD5 , bidir , 0, 133 , 0, Z),"& " 140 (BC_0, * , internal , X),"& " 141 (BC_1, RCLK1 , output2 , X),"& " 142 (BC_1, TSIG1 , input , X),"& " 143 (BC_1, TSER1 , input , X),"& " 144 (BC_1, TLINK1 , input , X),"& " 145 (BC_0, * , internal , X),"& " 146 (BC_1, TCLK1 , input , X),"& " 147 (BC_0, * , internal , X),"& " 148 (BC_0, * , internal , X),"& " 149 (BC_1, TCLKO1 , output2 , X),"& " 150 (BC_1, TPOSO1 , output2 , X),"& " 151 (BC_1, TNEGO1 , output2 , X),"& " 152 (BC_1, RCLKO1 , output2 , X),"& " 153 (BC_1, RLINK1 , output2 , X),"& " 154 (BC_7, TSYNC1 , bidir , 0, 155 , 0, Z),"& " 155 (BC_2, * , control , 0),"& " 156 (BC_1, TSSYNC1 , input , X),"& " 157 (BC_1, TLCLK1 , output2 , X),"& " 158 (BC_1, TCHCLK1 , output2 , X),"& " 159 (BC_1, TCHBLK1 , output2 , X),"& " 160 (BC_7, RSYNC1 , bidir , 0, 161 , 0, Z),"& " 161 (BC_2, * , control , 0),"& " 162 (BC_1, RSIGF1 , output2 , X),"& " 163 (BC_1, RMSYNC1 , output2 , X),"& " 164 (BC_1, RLOS_LOTC1 , output2 , X),"& " 165 (BC_1, RLCLK1 , output2 , X),"& " 166 (BC_1, RFSYNC1 , output2 , X),"& " 167 (BC_1, RCHCLK1 , output2 , X),"& " 168 (BC_1, RCHBLK1 , output2 , X),"& " 169 (BC_0, * , internal , X),"& " 170 (BC_0, * , internal , 0),"& " 171 (BC_0, * , internal , X),"& " 172 (BC_0, * , internal , 0),"& " 173 (BC_0, * , internal , X),"& " 174 (BC_0, * , internal , 0),"& " 175 (BC_1, RSIG1 , output2 , X),"& " 176 (BC_0, * , internal , X),"& " 177 (BC_0, * , internal , X),"& " 178 (BC_1, RNEGO1 , output2 , X),"& " 179 (BC_1, RPOSO1 , output2 , X),"& " 180 (BC_1, BPCLK1 , output2 , X),"& " 181 (BC_1, RSER1 , output2 , X),"& " 182 (BC_1, RSYSCLK1 , input , X),"& " 183 (BC_1, TSYSCLK1 , input , X),"& " 184 (BC_1, A8 , input , X),"& " 185 (BC_1, INT , output2 , X),"& " 186 (BC_1, A2 , input , X),"& " 187 (BC_1, A0 , input , X),"& " 188 (BC_1, A3 , input , X),"& " 189 (BC_7, D7_AD7 , bidir , 0, 133 , 0, Z),"& " 190 (BC_7, D6_AD6 , bidir , 0, 133 , 0, Z),"& " 191 (BC_1, A7_ALE_AS , input , X),"& " 192 (BC_0, * , internal , X),"& " 193 (BC_1, RCLK3 , output2 , X),"& " 194 (BC_1, TSIG3 , input , X),"& " 195 (BC_1, TSER3 , input , X),"& " 196 (BC_1, TLINK3 , input , X),"& " 197 (BC_0, * , internal , X),"& " 198 (BC_1, TCLK3 , input , X),"& " 199 (BC_0, * , internal , X),"& " 200 (BC_0, * , internal , X),"& " 201 (BC_1, TCLKO3 , output2 , X),"& " 202 (BC_1, TPOSO3 , output2 , X),"& " 203 (BC_1, TNEGO3 , output2 , X)"; end DS21458CSBGA;