-- *********************************************************************** -- BSDL file for design ds3152 -- Created by Synopsys Version 2000.11 (Nov 27, 2000) -- Designer: -- Company: Dallas Semiconductor -- Date: Thu Jan 9 10:48:37 2003 -- *********************************************************************** entity ds3152 is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "CSBGA_144"); -- This section declares all the ports in the design. port ( A0 : in bit; A1 : in bit; A2 : in bit; A3 : in bit; ALE : in bit; CS_N : in bit; E3M2 : in bit; E3MCLK : in bit; HIZ_N : in bit; HW : in bit; JTCLK : in bit; JTDI : in bit; JTMS : in bit; JTRST_N : in bit; LLB1 : in bit; LLB2 : in bit; MOT : in bit; RBIN : in bit; RCINV : in bit; RD_N : in bit; RJA1 : in bit; RJA2 : in bit; RLB2 : in bit; RMON1 : in bit; RMON2 : in bit; RST_N : in bit; RTS1_N : in bit; RTS2_N : in bit; RXN1 : linkage bit; RXN2 : linkage bit; RXP1 : linkage bit; RXP2 : linkage bit; STMCLK : in bit; STS2 : in bit; T3MCLK : in bit; TBIN : in bit; TCINV : in bit; TCLK1 : in bit; TCLK2 : in bit; TDSA2 : in bit; TDSB2 : in bit; TEST_N : in bit; TJA1 : in bit; TJA2 : in bit; TLBO2 : in bit; TNEG1 : in bit; TNEG2 : in bit; TPOS1 : in bit; TPOS2 : in bit; TTS1_N : in bit; TTS2_N : in bit; AD5 : inout bit; AD6 : inout bit; AD7 : inout bit; E3M1 : inout bit; RLB1 : inout bit; STS1 : inout bit; TDSA1 : inout bit; TDSB1 : inout bit; TLBO1 : inout bit; JTDO : out bit; PRBS1 : out bit; PRBS2 : out bit; RCLK1 : out bit; RCLK2 : out bit; RLOS1_N : out bit; RLOS2_N : out bit; RNEG1 : out bit; RNEG2 : out bit; RPOS1 : out bit; RPOS2 : out bit; TDM1_N : out bit; TDM2_N : out bit; TXN1 : linkage bit; TXN2 : linkage bit; TXP1 : linkage bit; TXP2 : linkage bit; AVDD1 : linkage bit; AVDD2 : linkage bit; NC : linkage bit_vector (1 to 41); VDD : linkage bit_vector (1 to 12); VSS : linkage bit_vector (1 to 12) ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of ds3152: entity is "STD_1149_1_1993"; attribute PIN_MAP of ds3152: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information -- is extracted from the port-to-pin map file that was read in using -- the "read_pin_map" command. constant CSBGA_144: PIN_MAP_STRING := "A0 : K6," & "A1 : L6," & "A2 : K7," & "A3 : L7," & "ALE : C7," & "CS_N : B7," & "E3M2 : G10," & "E3MCLK : E12," & "HIZ_N : J8," & "HW : E9," & "JTCLK : E4," & "JTDI : H4," & "JTMS : D5," & "JTRST_N : D4," & "LLB1 : B5," & "LLB2 : L8," & "MOT : C6," & "RBIN : D9," & "RCINV : J9," & "RD_N : B6," & "RJA1 : B4," & "RJA2 : L9," & "RLB2 : K8," & "RMON1 : A4," & "RMON2 : M9," & "RST_N : H1," & "RTS1_N : B2," & "RTS2_N : L11," & "RXN1 : A2," & "RXN2 : M11," & "RXP1 : A3," & "RXP2 : M10," & "STMCLK : M8," & "STS2 : G11," & "T3MCLK : A5," & "TBIN : D8," & "TCINV : H9," & "TCLK1 : E1," & "TCLK2 : H12," & "TDSA2 : F11," & "TDSB2 : F10," & "TEST_N : J5," & "TJA1 : C4," & "TJA2 : K9," & "TLBO2 : H10," & "TNEG1 : D2," & "TNEG2 : J11," & "TPOS1 : D1," & "TPOS2 : J12," & "TTS1_N : E2," & "TTS2_N : H11," & "AD5 : H2," & "AD6 : H3," & "AD7 : J3," & "E3M1 : F3," & "RLB1 : C5," & "STS1 : F2," & "TDSA1 : G2," & "TDSB1 : G3," & "TLBO1 : E3," & "JTDO : J4," & "PRBS1 : B1," & "PRBS2 : L12," & "RCLK1 : C1," & "RCLK2 : K12," & "RLOS1_N : A1," & "RLOS2_N : M12," & "RNEG1 : C3," & "RNEG2 : K10," & "RPOS1 : C2," & "RPOS2 : K11," & "TDM1_N : D3," & "TDM2_N : J10," & "TXN1 : G1," & "TXN2 : F12," & "TXP1 : F1," & "TXP2 : G12," & "AVDD1 : B3," & "AVDD2 : L10," & "NC : (A6, A7, A8, A9, A10, A11, A12, B8, B9, B10, B11, B12, C8" & ", C9, C10, C11, C12, D10, D11, D12, E10, E11, J1, J2, K1, K2, K3, " & "K4, K5, L1, L2, L3, L4, L5, M1, M2, M3, M4, M5, M6, M7)," & "VDD : (D6, E5, E6, F4, F5, F6, G7, G8, G9, H7, H8, J7)," & "VSS : (D7, E7, E8, F7, F8, F9, G4, G5, G6, H5, H6, J6)"; -- This section specifies the TAP ports. -- For the TAP TCK port, the parameters in the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of JTCLK : signal is (10.0e6, BOTH); attribute TAP_SCAN_IN of JTDI : signal is true; attribute TAP_SCAN_MODE of JTMS : signal is true; attribute TAP_SCAN_OUT of JTDO : signal is true; attribute TAP_SCAN_RESET of JTRST_N: signal is true; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of ds3152: entity is 3; -- Specifies the boundary-scan instructions implemented in the -- design and their opcodes. attribute INSTRUCTION_OPCODE of ds3152: entity is "BYPASS (111)," & "EXTEST (000)," & "SAMPLE (010)," & "CLAMP (011)," & "USER1 (100)," & "USER2 (101)," & "USER3 (110)," & "IDCODE (001)"; -- Specifies the bit pattern that is loaded into the instruction -- register when the TAP controller passes through the Capture-IR -- state. The standard mandates that the two LSBs must be "01". -- The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of ds3152: entity is "001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID -- register during the IDCODE instruction when the TAP controller -- passes through the Capture-DR state. attribute IDCODE_REGISTER of ds3152: entity is "0001" & -- 4-bit version number "0000000000110000" & -- 16-bit part number "00010100001" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 -- This section specifies the test data register placed between TDI -- and TDO for each implemented instruction. attribute REGISTER_ACCESS of ds3152: entity is "BYPASS (BYPASS, CLAMP, USER1, USER2, USER3)," & "BOUNDARY (EXTEST, SAMPLE)," & "DEVICE_ID (IDCODE)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of ds3152: entity is 114; -- The following list specifies the characteristics of each cell -- in the boundary scan register from TDI to TDO. -- The following is a description of the label fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not -- have a port name. -- function: Is the function of the cell as defined by the -- standard. Is one of input, output2, output3, -- bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be -- loaded with for safe operation when the software -- might otherwise choose a random value. -- ccell : The control cell number. Specifies the control -- cell that drives the output enable for this port. -- disval : Specifies the value that is loaded into the -- control cell to disable the output enable for -- the corresponding port. -- rslt : Resulting state. Shows the state of the driver -- when it is disabled. attribute BOUNDARY_REGISTER of ds3152: entity is -- -- num cell port function safe [ccell disval rslt] -- "113 (BC_4, TCLK1, observe_only, X), " & "112 (BC_4, TPOS1, observe_only, X), " & "111 (BC_4, TNEG1, observe_only, X), " & "110 (BC_4, TDSA1, observe_only, X), " & "109 (BC_2, TDSA1, output3, X, 104, 1, Z), " & "108 (BC_4, TDSB1, observe_only, X), " & "107 (BC_2, TDSB1, output3, X, 104, 1, Z), " & "106 (BC_4, TLBO1, observe_only, X), " & "105 (BC_2, TLBO1, output3, X, 104, 1, Z), " & "104 (BC_2, *, controlr, 1), " & "103 (BC_4, TTS1_N, observe_only, X), " & "102 (BC_4, TJA1, observe_only, X), " & "101 (BC_4, RMON1, observe_only, X), " & "100 (BC_4, RTS1_N, observe_only, X), " & "99 (BC_4, RJA1, observe_only, X), " & "98 (BC_4, LLB1, observe_only, X), " & "97 (BC_4, RLB1, observe_only, X), " & "96 (BC_2, RLB1, output3, X, 95, 1, Z), " & "95 (BC_2, *, controlr, 1), " & "94 (BC_4, E3M1, observe_only, X), " & "93 (BC_2, E3M1, output3, X, 104, 1, Z), " & "92 (BC_4, STS1, observe_only, X), " & "91 (BC_2, STS1, output3, X, 104, 1, Z), " & "90 (BC_2, TDM1_N, output3, X, 87, 1, Z), " & "89 (BC_2, RLOS1_N, output3, X, 87, 1, Z), " & "88 (BC_2, PRBS1, output3, X, 87, 1, Z), " & "87 (BC_2, *, controlr, 1), " & "86 (BC_2, RCLK1, output3, X, 83, 1, Z), " & "85 (BC_2, RPOS1, output3, X, 83, 1, Z), " & "84 (BC_2, RNEG1, output3, X, 83, 1, Z), " & "83 (BC_2, *, controlr, 1), " & "82 (BC_4, TCLK2, observe_only, X), " & "81 (BC_4, TPOS2, observe_only, X), " & "80 (BC_4, TNEG2, observe_only, X), " & "79 (BC_4, TDSA2, observe_only, X), " & "78 (BC_4, TDSB2, observe_only, X), " & "77 (BC_4, TLBO2, observe_only, X), " & "76 (BC_4, TTS2_N, observe_only, X), " & "75 (BC_4, TJA2, observe_only, X), " & "74 (BC_4, RMON2, observe_only, X), " & "73 (BC_4, RTS2_N, observe_only, X), " & "72 (BC_4, RJA2, observe_only, X), " & "71 (BC_4, LLB2, observe_only, X), " & "70 (BC_4, RLB2, observe_only, X), " & "69 (BC_4, E3M2, observe_only, X), " & "68 (BC_4, STS2, observe_only, X), " & "67 (BC_2, TDM2_N, output3, X, 64, 1, Z), " & "66 (BC_2, RLOS2_N, output3, X, 64, 1, Z), " & "65 (BC_2, PRBS2, output3, X, 64, 1, Z), " & "64 (BC_2, *, controlr, 1), " & "63 (BC_2, RCLK2, output3, X, 60, 1, Z), " & "62 (BC_2, RPOS2, output3, X, 60, 1, Z), " & "61 (BC_2, RNEG2, output3, X, 60, 1, Z), " & "60 (BC_2, *, controlr, 1), " & "59 (BC_0, *, internal, X), " & "58 (BC_0, *, internal, X), " & "57 (BC_0, *, internal, X), " & "56 (BC_4, RD_N, observe_only, X), " & "55 (BC_4, MOT, observe_only, X), " & "54 (BC_0, *, internal, X), " & "53 (BC_0, *, internal, X), " & "52 (BC_0, *, internal, X), " & "51 (BC_0, *, internal, X), " & "50 (BC_0, *, internal, X), " & "49 (BC_0, *, internal, X), " & "48 (BC_0, *, internal, X), " & "47 (BC_0, *, internal, X), " & "46 (BC_4, ALE, observe_only, X), " & "45 (BC_4, CS_N, observe_only, X), " & "44 (BC_0, *, internal, X), " & "43 (BC_0, *, internal, X), " & "42 (BC_0, *, internal, X), " & "41 (BC_0, *, internal, X), " & "40 (BC_0, *, internal, X), " & "39 (BC_0, *, internal, X), " & "38 (BC_0, *, internal, X), " & "37 (BC_0, *, internal, X), " & "36 (BC_0, *, internal, X), " & "35 (BC_0, *, internal, X), " & "34 (BC_0, *, internal, X), " & "33 (BC_4, A3, observe_only, X), " & "32 (BC_4, A2, observe_only, X), " & "31 (BC_0, *, internal, X), " & "30 (BC_0, *, internal, X), " & "29 (BC_4, AD7, observe_only, X), " & "28 (BC_2, AD7, output3, X, 104, 1, Z), " & "27 (BC_0, *, internal, X), " & "26 (BC_0, *, internal, X), " & "25 (BC_0, *, internal, X), " & "24 (BC_4, AD5, observe_only, X), " & "23 (BC_2, AD5, output3, X, 104, 1, Z), " & "22 (BC_4, AD6, observe_only, X), " & "21 (BC_2, AD6, output3, X, 104, 1, Z), " & "20 (BC_4, A0, observe_only, X), " & "19 (BC_4, A1, observe_only, X), " & "18 (BC_0, *, internal, X), " & "17 (BC_0, *, internal, X), " & "16 (BC_0, *, internal, X), " & "15 (BC_0, *, internal, X), " & "14 (BC_0, *, internal, X), " & "13 (BC_0, *, internal, X), " & "12 (BC_0, *, internal, X), " & "11 (BC_0, *, internal, X), " & "10 (BC_4, T3MCLK, observe_only, X), " & "9 (BC_4, E3MCLK, observe_only, X), " & "8 (BC_4, STMCLK, observe_only, X), " & "7 (BC_4, RST_N, observe_only, X), " & "6 (BC_4, HIZ_N, observe_only, X), " & "5 (BC_4, TEST_N, observe_only, X), " & "4 (BC_4, HW, observe_only, X), " & "3 (BC_4, RBIN, observe_only, X), " & "2 (BC_4, TBIN, observe_only, X), " & "1 (BC_4, RCINV, observe_only, X), " & "0 (BC_4, TCINV, observe_only, X) "; end ds3152;