-- *********************************************************************** -- BSDL file for design DS3148_BGA_256 -- Created by Synopsys Version 2000.11 (Nov 27, 2000) -- Designer: -- Company: Dallas Semiconductor -- Date: Tue May 14 14:09:59 2002 -- *********************************************************************** entity DS3148_BGA_256 is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "BGA_256"); -- This section declares all the ports in the design. port ( ADDR0 : in bit; ADDR1 : in bit; ADDR10 : in bit; ADDR11 : in bit; ADDR2 : in bit; ADDR3 : in bit; ADDR4 : in bit; ADDR5 : in bit; ADDR6 : in bit; ADDR7 : in bit; ADDR8 : in bit; ADDR9 : in bit; ALE : in bit; CS_N : in bit; HIZ_N : in bit; JTCLK : in bit; JTDI : in bit; JTMS : in bit; JTRST_N : in bit; MOT : in bit; RCLK1 : in bit; RCLK2 : in bit; RCLK3 : in bit; RCLK4 : in bit; RCLK5 : in bit; RCLK6 : in bit; RCLK7 : in bit; RCLK8 : in bit; RD_N : in bit; RECU : in bit; RNEG1 : in bit; RNEG2 : in bit; RNEG3 : in bit; RNEG4 : in bit; RNEG5 : in bit; RNEG6 : in bit; RNEG7 : in bit; RNEG8 : in bit; RPOS1 : in bit; RPOS2 : in bit; RPOS3 : in bit; RPOS4 : in bit; RPOS5 : in bit; RPOS6 : in bit; RPOS7 : in bit; RPOS8 : in bit; RST_N : in bit; SCLK : in bit; TCCLK : in bit; TCSEL : in bit; TDAT1 : in bit; TDAT2 : in bit; TDAT3 : in bit; TDAT4 : in bit; TDAT5 : in bit; TDAT6 : in bit; TDAT7 : in bit; TDAT8 : in bit; TEST_N : in bit; TICLK1 : in bit; TICLK2 : in bit; TICLK3 : in bit; TICLK4 : in bit; TICLK5 : in bit; TICLK6 : in bit; TICLK7 : in bit; TICLK8 : in bit; TMEI : in bit; TOH1 : in bit; TOH2 : in bit; TOH3 : in bit; TOH4 : in bit; TOH5 : in bit; TOH6 : in bit; TOH7 : in bit; TOH8 : in bit; TOHEN1 : in bit; TOHEN2 : in bit; TOHEN3 : in bit; TOHEN4 : in bit; TOHEN5 : in bit; TOHEN6 : in bit; TOHEN7 : in bit; TOHEN8 : in bit; WR_N : in bit; DATA0 : inout bit; DATA1 : inout bit; DATA2 : inout bit; DATA3 : inout bit; DATA4 : inout bit; DATA5 : inout bit; DATA6 : inout bit; DATA7 : inout bit; INT_N : inout bit; TSOF1 : inout bit; TSOF2 : inout bit; TSOF3 : inout bit; TSOF4 : inout bit; TSOF5 : inout bit; TSOF6 : inout bit; TSOF7 : inout bit; TSOF8 : inout bit; JTDO : out bit; RDAT1 : out bit; RDAT2 : out bit; RDAT3 : out bit; RDAT4 : out bit; RDAT5 : out bit; RDAT6 : out bit; RDAT7 : out bit; RDAT8 : out bit; RDEN1 : out bit; RDEN2 : out bit; RDEN3 : out bit; RDEN4 : out bit; RDEN5 : out bit; RDEN6 : out bit; RDEN7 : out bit; RDEN8 : out bit; RLOS1 : out bit; RLOS2 : out bit; RLOS3 : out bit; RLOS4 : out bit; RLOS5 : out bit; RLOS6 : out bit; RLOS7 : out bit; RLOS8 : out bit; ROCLK1 : out bit; ROCLK2 : out bit; ROCLK3 : out bit; ROCLK4 : out bit; ROCLK5 : out bit; ROCLK6 : out bit; ROCLK7 : out bit; ROCLK8 : out bit; ROOF1 : out bit; ROOF2 : out bit; ROOF3 : out bit; ROOF4 : out bit; ROOF5 : out bit; ROOF6 : out bit; ROOF7 : out bit; ROOF8 : out bit; RSOF1 : out bit; RSOF2 : out bit; RSOF3 : out bit; RSOF4 : out bit; RSOF5 : out bit; RSOF6 : out bit; RSOF7 : out bit; RSOF8 : out bit; TCLK1 : out bit; TCLK2 : out bit; TCLK3 : out bit; TCLK4 : out bit; TCLK5 : out bit; TCLK6 : out bit; TCLK7 : out bit; TCLK8 : out bit; TDEN1 : out bit; TDEN2 : out bit; TDEN3 : out bit; TDEN4 : out bit; TDEN5 : out bit; TDEN6 : out bit; TDEN7 : out bit; TDEN8 : out bit; TNEG1 : out bit; TNEG2 : out bit; TNEG3 : out bit; TNEG4 : out bit; TNEG5 : out bit; TNEG6 : out bit; TNEG7 : out bit; TNEG8 : out bit; TPOS1 : out bit; TPOS2 : out bit; TPOS3 : out bit; TPOS4 : out bit; TPOS5 : out bit; TPOS6 : out bit; TPOS7 : out bit; TPOS8 : out bit; NC : linkage bit; VDD : linkage bit_vector (1 to 36); VSS : linkage bit_vector (1 to 36) ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of DS3148_BGA_256: entity is "STD_1149_1_1993"; attribute PIN_MAP of DS3148_BGA_256: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information -- is extracted from the port-to-pin map file that was read in using -- the "read_pin_map" command. constant BGA_256: PIN_MAP_STRING := "ADDR0 : P3," & "ADDR1 : R1," & "ADDR10 : V16," & "ADDR11 : U16," & "ADDR2 : R3," & "ADDR3 : T1," & "ADDR4 : T3," & "ADDR5 : V14," & "ADDR6 : Y15," & "ADDR7 : V15," & "ADDR8 : Y16," & "ADDR9 : W16," & "ALE : F20," & "CS_N : G18," & "HIZ_N : D5," & "JTCLK : A6," & "JTDI : B6," & "JTMS : C7," & "JTRST_N : C6," & "MOT : E17," & "RCLK1 : D2," & "RCLK2 : N2," & "RCLK3 : W4," & "RCLK4 : U19," & "RCLK5 : H19," & "RCLK6 : B17," & "RCLK7 : W13," & "RCLK8 : B8," & "RD_N : F18," & "RECU : B5," & "RNEG1 : C3," & "RNEG2 : M3," & "RNEG3 : V3," & "RNEG4 : V18," & "RNEG5 : J18," & "RNEG6 : C18," & "RNEG7 : V12," & "RNEG8 : C9," & "RPOS1 : C2," & "RPOS2 : M4," & "RPOS3 : W3," & "RPOS4 : V19," & "RPOS5 : J17," & "RPOS6 : B18," & "RPOS7 : U12," & "RPOS8 : D9," & "RST_N : A5," & "SCLK : E19," & "TCCLK : E20," & "TCSEL : F17," & "TDAT1 : D4," & "TDAT2 : K1," & "TDAT3 : U4," & "TDAT4 : U17," & "TDAT5 : L20," & "TDAT6 : D17," & "TDAT7 : Y10," & "TDAT8 : A11," & "TEST_N : D6," & "TICLK1 : C4," & "TICLK2 : K2," & "TICLK3 : U3," & "TICLK4 : V17," & "TICLK5 : L19," & "TICLK6 : D18," & "TICLK7 : W10," & "TICLK8 : B11," & "TMEI : C5," & "TOH1 : B4," & "TOH2 : K3," & "TOH3 : U2," & "TOH4 : W17," & "TOH5 : L18," & "TOH6 : D19," & "TOH7 : V10," & "TOH8 : C11," & "TOHEN1 : A4," & "TOHEN2 : K4," & "TOHEN3 : U1," & "TOHEN4 : Y17," & "TOHEN5 : L17," & "TOHEN6 : D20," & "TOHEN7 : U10," & "TOHEN8 : D11," & "WR_N : F19," & "DATA0 : P4," & "DATA1 : R2," & "DATA2 : R4," & "DATA3 : T2," & "DATA4 : T4," & "DATA5 : U14," & "DATA6 : W15," & "DATA7 : U15," & "INT_N : E18," & "TSOF1 : B3," & "TSOF2 : L3," & "TSOF3 : V2," & "TSOF4 : W18," & "TSOF5 : K18," & "TSOF6 : C19," & "TSOF7 : V11," & "TSOF8 : C10," & "JTDO : D7," & "RDAT1 : D1," & "RDAT2 : N4," & "RDAT3 : Y4," & "RDAT4 : U20," & "RDAT5 : H17," & "RDAT6 : A17," & "RDAT7 : U13," & "RDAT8 : D8," & "RDEN1 : E4," & "RDEN2 : P1," & "RDEN3 : U5," & "RDEN4 : T17," & "RDEN5 : G20," & "RDEN6 : D16," & "RDEN7 : Y14," & "RDEN8 : A7," & "RLOS1 : B1," & "RLOS2 : M2," & "RLOS3 : Y2," & "RLOS4 : W20," & "RLOS5 : J19," & "RLOS6 : A19," & "RLOS7 : W12," & "RLOS8 : B9," & "ROCLK1 : E3," & "ROCLK2 : P2," & "ROCLK3 : V5," & "ROCLK4 : T18," & "ROCLK5 : G19," & "ROCLK6 : C16," & "ROCLK7 : W14," & "ROCLK8 : B7," & "ROOF1 : D3," & "ROOF2 : N1," & "ROOF3 : V4," & "ROOF4 : U18," & "ROOF5 : H20," & "ROOF6 : C17," & "ROOF7 : Y13," & "ROOF8 : A8," & "RSOF1 : C1," & "RSOF2 : N3," & "RSOF3 : Y3," & "RSOF4 : V20," & "RSOF5 : H18," & "RSOF6 : A18," & "RSOF7 : V13," & "RSOF8 : C8," & "TCLK1 : A2," & "TCLK2 : L2," & "TCLK3 : W1," & "TCLK4 : Y19," & "TCLK5 : K19," & "TCLK6 : B20," & "TCLK7 : W11," & "TCLK8 : B10," & "TDEN1 : A3," & "TDEN2 : L1," & "TDEN3 : V1," & "TDEN4 : Y18," & "TDEN5 : K20," & "TDEN6 : C20," & "TDEN7 : Y11," & "TDEN8 : A10," & "TNEG1 : B2," & "TNEG2 : L4," & "TNEG3 : W2," & "TNEG4 : W19," & "TNEG5 : K17," & "TNEG6 : B19," & "TNEG7 : U11," & "TNEG8 : D10," & "TPOS1 : A1," & "TPOS2 : M1," & "TPOS3 : Y1," & "TPOS4 : Y20," & "TPOS5 : J20," & "TPOS6 : A20," & "TPOS7 : Y12," & "TPOS8 : A9," & "NC : G17," & "VDD : (E5, F5, G5, H5, J5, M5, N5, P5, T5, R5, T6, T7, T8, T9, " & "T12, T13, T14, T15, T16, R16, P16, N16, M16, J16, H16, G16, F16, " & "E16, E15, E14, E13, E12, E6, E7, E8, E9)," & "VSS : (F6, G6, K5, L5, P6, J9, K9, L9, M9, R6, R7, T10, T11, " & "R14, J10, K10, L10, M10, R15, P15, L16, K16, G15, J11, K11, L11, " & "M11, F15, F14, E11, E10, F7, J12, K12, L12, M12)"; -- This section specifies the TAP ports. -- For the TAP TCK port, the parameters in the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of JTCLK : signal is (10.0e6, BOTH); attribute TAP_SCAN_IN of JTDI : signal is true; attribute TAP_SCAN_MODE of JTMS : signal is true; attribute TAP_SCAN_OUT of JTDO : signal is true; attribute TAP_SCAN_RESET of JTRST_N: signal is true; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of DS3148_BGA_256: entity is 3; -- Specifies the boundary-scan instructions implemented in the -- design and their opcodes. attribute INSTRUCTION_OPCODE of DS3148_BGA_256: entity is "BYPASS (111)," & "EXTEST (000)," & "SAMPLE (010)," & "CLAMP (011)," & "HIGHZ (100)," & "USER1 (101)," & "USER2 (110)," & "IDCODE (001)"; -- Specifies the bit pattern that is loaded into the instruction -- register when the TAP controller passes through the Capture-IR -- state. The standard mandates that the two LSBs must be "01". -- The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of DS3148_BGA_256: entity is "001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID -- register during the IDCODE instruction when the TAP controller -- passes through the Capture-DR state. attribute IDCODE_REGISTER of DS3148_BGA_256: entity is "0001" & -- 4-bit version number "0000000000010110" & -- 16-bit part number "00010100001" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 -- This section specifies the test data register placed between TDI -- and TDO for each implemented instruction. attribute REGISTER_ACCESS of DS3148_BGA_256: entity is "BYPASS (BYPASS, CLAMP, HIGHZ, USER1, USER2)," & "BOUNDARY (EXTEST, SAMPLE)," & "DEVICE_ID (IDCODE)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of DS3148_BGA_256: entity is 220; -- The following list specifies the characteristics of each cell -- in the boundary scan register from TDI to TDO. -- The following is a description of the label fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not -- have a port name. -- function: Is the function of the cell as defined by the -- standard. Is one of input, output2, output3, -- bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be -- loaded with for safe operation when the software -- might otherwise choose a random value. -- ccell : The control cell number. Specifies the control -- cell that drives the output enable for this port. -- disval : Specifies the value that is loaded into the -- control cell to disable the output enable for -- the corresponding port. -- rslt : Resulting state. Shows the state of the driver -- when it is disabled. attribute BOUNDARY_REGISTER of DS3148_BGA_256: entity is -- -- num cell port function safe [ccell disval rslt] -- "219 (BC_4, TOHEN1, observe_only, X), " & "218 (BC_4, TOH1, observe_only, X), " & "217 (BC_4, TICLK1, observe_only, X), " & "216 (BC_4, TDAT1, observe_only, X), " & "215 (BC_2, TDEN1, output3, X, 214, 1, Z), " & "214 (BC_2, *, controlr, 1), " & "213 (BC_2, TCLK1, output3, X, 214, 1, Z), " & "212 (BC_4, TSOF1, observe_only, X), " & "211 (BC_2, TSOF1, output3, X, 210, 1, Z), " & "210 (BC_2, *, controlr, 1), " & "209 (BC_2, TNEG1, output3, X, 214, 1, Z), " & "208 (BC_2, TPOS1, output3, X, 214, 1, Z), " & "207 (BC_2, RLOS1, output3, X, 214, 1, Z), " & "206 (BC_4, RNEG1, observe_only, X), " & "205 (BC_4, RPOS1, observe_only, X), " & "204 (BC_2, ROOF1, output3, X, 214, 1, Z), " & "203 (BC_4, RCLK1, observe_only, X), " & "202 (BC_2, RSOF1, output3, X, 214, 1, Z), " & "201 (BC_2, RDAT1, output3, X, 214, 1, Z), " & "200 (BC_2, RDEN1, output3, X, 214, 1, Z), " & "199 (BC_2, ROCLK1, output3, X, 214, 1, Z), " & "198 (BC_4, TOHEN2, observe_only, X), " & "197 (BC_4, TOH2, observe_only, X), " & "196 (BC_4, TICLK2, observe_only, X), " & "195 (BC_4, TDAT2, observe_only, X), " & "194 (BC_2, TDEN2, output3, X, 193, 1, Z), " & "193 (BC_2, *, controlr, 1), " & "192 (BC_2, TCLK2, output3, X, 193, 1, Z), " & "191 (BC_4, TSOF2, observe_only, X), " & "190 (BC_2, TSOF2, output3, X, 189, 1, Z), " & "189 (BC_2, *, controlr, 1), " & "188 (BC_2, TNEG2, output3, X, 193, 1, Z), " & "187 (BC_2, TPOS2, output3, X, 193, 1, Z), " & "186 (BC_2, RLOS2, output3, X, 193, 1, Z), " & "185 (BC_4, RNEG2, observe_only, X), " & "184 (BC_4, RPOS2, observe_only, X), " & "183 (BC_2, ROOF2, output3, X, 193, 1, Z), " & "182 (BC_4, RCLK2, observe_only, X), " & "181 (BC_2, RSOF2, output3, X, 193, 1, Z), " & "180 (BC_2, RDAT2, output3, X, 193, 1, Z), " & "179 (BC_2, RDEN2, output3, X, 193, 1, Z), " & "178 (BC_2, ROCLK2, output3, X, 193, 1, Z), " & "177 (BC_4, ADDR0, observe_only, X), " & "176 (BC_4, DATA0, observe_only, X), " & "175 (BC_2, DATA0, output3, X, 174, 1, Z), " & "174 (BC_2, *, controlr, 1), " & "173 (BC_4, ADDR1, observe_only, X), " & "172 (BC_4, DATA1, observe_only, X), " & "171 (BC_2, DATA1, output3, X, 170, 1, Z), " & "170 (BC_2, *, controlr, 1), " & "169 (BC_4, ADDR2, observe_only, X), " & "168 (BC_4, DATA2, observe_only, X), " & "167 (BC_2, DATA2, output3, X, 166, 1, Z), " & "166 (BC_2, *, controlr, 1), " & "165 (BC_4, ADDR3, observe_only, X), " & "164 (BC_4, DATA3, observe_only, X), " & "163 (BC_2, DATA3, output3, X, 162, 1, Z), " & "162 (BC_2, *, controlr, 1), " & "161 (BC_4, ADDR4, observe_only, X), " & "160 (BC_4, DATA4, observe_only, X), " & "159 (BC_2, DATA4, output3, X, 158, 1, Z), " & "158 (BC_2, *, controlr, 1), " & "157 (BC_4, TOHEN3, observe_only, X), " & "156 (BC_4, TOH3, observe_only, X), " & "155 (BC_4, TICLK3, observe_only, X), " & "154 (BC_4, TDAT3, observe_only, X), " & "153 (BC_2, TDEN3, output3, X, 152, 1, Z), " & "152 (BC_2, *, controlr, 1), " & "151 (BC_2, TCLK3, output3, X, 152, 1, Z), " & "150 (BC_4, TSOF3, observe_only, X), " & "149 (BC_2, TSOF3, output3, X, 148, 1, Z), " & "148 (BC_2, *, controlr, 1), " & "147 (BC_2, TNEG3, output3, X, 152, 1, Z), " & "146 (BC_2, TPOS3, output3, X, 152, 1, Z), " & "145 (BC_2, RLOS3, output3, X, 152, 1, Z), " & "144 (BC_4, RNEG3, observe_only, X), " & "143 (BC_4, RPOS3, observe_only, X), " & "142 (BC_2, ROOF3, output3, X, 152, 1, Z), " & "141 (BC_4, RCLK3, observe_only, X), " & "140 (BC_2, RSOF3, output3, X, 152, 1, Z), " & "139 (BC_2, RDAT3, output3, X, 152, 1, Z), " & "138 (BC_2, RDEN3, output3, X, 152, 1, Z), " & "137 (BC_2, ROCLK3, output3, X, 152, 1, Z), " & "136 (BC_4, TOHEN7, observe_only, X), " & "135 (BC_4, TOH7, observe_only, X), " & "134 (BC_4, TICLK7, observe_only, X), " & "133 (BC_4, TDAT7, observe_only, X), " & "132 (BC_2, TDEN7, output3, X, 131, 1, Z), " & "131 (BC_2, *, controlr, 1), " & "130 (BC_2, TCLK7, output3, X, 131, 1, Z), " & "129 (BC_4, TSOF7, observe_only, X), " & "128 (BC_2, TSOF7, output3, X, 127, 1, Z), " & "127 (BC_2, *, controlr, 1), " & "126 (BC_2, TNEG7, output3, X, 131, 1, Z), " & "125 (BC_2, TPOS7, output3, X, 131, 1, Z), " & "124 (BC_2, RLOS7, output3, X, 131, 1, Z), " & "123 (BC_4, RNEG7, observe_only, X), " & "122 (BC_4, RPOS7, observe_only, X), " & "121 (BC_2, ROOF7, output3, X, 131, 1, Z), " & "120 (BC_4, RCLK7, observe_only, X), " & "119 (BC_2, RSOF7, output3, X, 131, 1, Z), " & "118 (BC_2, RDAT7, output3, X, 131, 1, Z), " & "117 (BC_2, RDEN7, output3, X, 131, 1, Z), " & "116 (BC_2, ROCLK7, output3, X, 131, 1, Z), " & "115 (BC_4, ADDR5, observe_only, X), " & "114 (BC_4, DATA5, observe_only, X), " & "113 (BC_2, DATA5, output3, X, 112, 1, Z), " & "112 (BC_2, *, controlr, 1), " & "111 (BC_4, ADDR6, observe_only, X), " & "110 (BC_4, DATA6, observe_only, X), " & "109 (BC_2, DATA6, output3, X, 108, 1, Z), " & "108 (BC_2, *, controlr, 1), " & "107 (BC_4, ADDR7, observe_only, X), " & "106 (BC_4, DATA7, observe_only, X), " & "105 (BC_2, DATA7, output3, X, 104, 1, Z), " & "104 (BC_2, *, controlr, 1), " & "103 (BC_4, ADDR8, observe_only, X), " & "102 (BC_4, ADDR9, observe_only, X), " & "101 (BC_4, ADDR10, observe_only, X), " & "100 (BC_4, ADDR11, observe_only, X), " & "99 (BC_4, TOHEN4, observe_only, X), " & "98 (BC_4, TOH4, observe_only, X), " & "97 (BC_4, TICLK4, observe_only, X), " & "96 (BC_4, TDAT4, observe_only, X), " & "95 (BC_2, TDEN4, output3, X, 94, 1, Z), " & "94 (BC_2, *, controlr, 1), " & "93 (BC_2, TCLK4, output3, X, 94, 1, Z), " & "92 (BC_4, TSOF4, observe_only, X), " & "91 (BC_2, TSOF4, output3, X, 90, 1, Z), " & "90 (BC_2, *, controlr, 1), " & "89 (BC_2, TNEG4, output3, X, 94, 1, Z), " & "88 (BC_2, TPOS4, output3, X, 94, 1, Z), " & "87 (BC_2, RLOS4, output3, X, 94, 1, Z), " & "86 (BC_4, RNEG4, observe_only, X), " & "85 (BC_4, RPOS4, observe_only, X), " & "84 (BC_2, ROOF4, output3, X, 94, 1, Z), " & "83 (BC_4, RCLK4, observe_only, X), " & "82 (BC_2, RSOF4, output3, X, 94, 1, Z), " & "81 (BC_2, RDAT4, output3, X, 94, 1, Z), " & "80 (BC_2, RDEN4, output3, X, 94, 1, Z), " & "79 (BC_2, ROCLK4, output3, X, 94, 1, Z), " & "78 (BC_4, TOHEN5, observe_only, X), " & "77 (BC_4, TOH5, observe_only, X), " & "76 (BC_4, TICLK5, observe_only, X), " & "75 (BC_4, TDAT5, observe_only, X), " & "74 (BC_2, TDEN5, output3, X, 73, 1, Z), " & "73 (BC_2, *, controlr, 1), " & "72 (BC_2, TCLK5, output3, X, 73, 1, Z), " & "71 (BC_4, TSOF5, observe_only, X), " & "70 (BC_2, TSOF5, output3, X, 69, 1, Z), " & "69 (BC_2, *, controlr, 1), " & "68 (BC_2, TNEG5, output3, X, 73, 1, Z), " & "67 (BC_2, TPOS5, output3, X, 73, 1, Z), " & "66 (BC_2, RLOS5, output3, X, 73, 1, Z), " & "65 (BC_4, RNEG5, observe_only, X), " & "64 (BC_4, RPOS5, observe_only, X), " & "63 (BC_2, ROOF5, output3, X, 73, 1, Z), " & "62 (BC_4, RCLK5, observe_only, X), " & "61 (BC_2, RSOF5, output3, X, 73, 1, Z), " & "60 (BC_2, RDAT5, output3, X, 73, 1, Z), " & "59 (BC_2, RDEN5, output3, X, 73, 1, Z), " & "58 (BC_2, ROCLK5, output3, X, 73, 1, Z), " & "57 (BC_4, CS_N, observe_only, X), " & "56 (BC_4, ALE, observe_only, X), " & "55 (BC_4, WR_N, observe_only, X), " & "54 (BC_4, RD_N, observe_only, X), " & "53 (BC_4, TCSEL, observe_only, X), " & "52 (BC_4, TCCLK, observe_only, X), " & "51 (BC_4, SCLK, observe_only, X), " & "50 (BC_4, INT_N, observe_only, X), " & "49 (BC_0, *, internal, X), " & "48 (BC_2, INT_N, output2, 1, 48, 1, WEAK1)," & "47 (BC_4, MOT, observe_only, X), " & "46 (BC_4, TOHEN6, observe_only, X), " & "45 (BC_4, TOH6, observe_only, X), " & "44 (BC_4, TICLK6, observe_only, X), " & "43 (BC_4, TDAT6, observe_only, X), " & "42 (BC_2, TDEN6, output3, X, 41, 1, Z), " & "41 (BC_2, *, controlr, 1), " & "40 (BC_2, TCLK6, output3, X, 41, 1, Z), " & "39 (BC_4, TSOF6, observe_only, X), " & "38 (BC_2, TSOF6, output3, X, 37, 1, Z), " & "37 (BC_2, *, controlr, 1), " & "36 (BC_2, TNEG6, output3, X, 41, 1, Z), " & "35 (BC_2, TPOS6, output3, X, 41, 1, Z), " & "34 (BC_2, RLOS6, output3, X, 41, 1, Z), " & "33 (BC_4, RNEG6, observe_only, X), " & "32 (BC_4, RPOS6, observe_only, X), " & "31 (BC_2, ROOF6, output3, X, 41, 1, Z), " & "30 (BC_4, RCLK6, observe_only, X), " & "29 (BC_2, RSOF6, output3, X, 41, 1, Z), " & "28 (BC_2, RDAT6, output3, X, 41, 1, Z), " & "27 (BC_2, RDEN6, output3, X, 41, 1, Z), " & "26 (BC_2, ROCLK6, output3, X, 41, 1, Z), " & "25 (BC_4, TOHEN8, observe_only, X), " & "24 (BC_4, TOH8, observe_only, X), " & "23 (BC_4, TICLK8, observe_only, X), " & "22 (BC_4, TDAT8, observe_only, X), " & "21 (BC_2, TDEN8, output3, X, 20, 1, Z), " & "20 (BC_2, *, controlr, 1), " & "19 (BC_2, TCLK8, output3, X, 20, 1, Z), " & "18 (BC_4, TSOF8, observe_only, X), " & "17 (BC_2, TSOF8, output3, X, 16, 1, Z), " & "16 (BC_2, *, controlr, 1), " & "15 (BC_2, TNEG8, output3, X, 20, 1, Z), " & "14 (BC_2, TPOS8, output3, X, 20, 1, Z), " & "13 (BC_2, RLOS8, output3, X, 20, 1, Z), " & "12 (BC_4, RNEG8, observe_only, X), " & "11 (BC_4, RPOS8, observe_only, X), " & "10 (BC_2, ROOF8, output3, X, 20, 1, Z), " & "9 (BC_4, RCLK8, observe_only, X), " & "8 (BC_2, RSOF8, output3, X, 20, 1, Z), " & "7 (BC_2, RDAT8, output3, X, 20, 1, Z), " & "6 (BC_2, RDEN8, output3, X, 20, 1, Z), " & "5 (BC_2, ROCLK8, output3, X, 20, 1, Z), " & "4 (BC_4, TEST_N, observe_only, X), " & "3 (BC_4, RST_N, observe_only, X), " & "2 (BC_4, RECU, observe_only, X), " & "1 (BC_4, TMEI, observe_only, X), " & "0 (BC_4, HIZ_N, observe_only, X) "; end DS3148_BGA_256;