-- *********************************************************************** -- BSDL file for design ds3131_top -- Created by Synopsys Version 2000.11 (Nov 27, 2000) -- Designer: -- Company: -- Date: Thu Oct 18 15:35:35 2001 -- *********************************************************************** entity ds3131_top is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "PBGA_256"); -- This section declares all the ports in the design. port ( jtclk : in bit; jtdi : in bit; jtms : in bit; jtrst : in bit; lbpxs : in bit; lcs_rc38 : in bit; lhlda_tc38 : in bit; lim_tc36 : in bit; lms_rd39 : in bit; lrdy_tc39 : in bit; pclk : in bit; pgnt : in bit; pidsel : in bit; prst : in bit; sen_n : in bit; smode_n : in bit; testmode_n : in bit; rc : in bit_vector (0 to 27); rd : in bit_vector (0 to 27); tc : in bit_vector (0 to 27); la0_rd37 : inout bit; la10_rd32 : inout bit; la11_rc32 : inout bit; la12_rd31 : inout bit; la13_rc31 : inout bit; la14_rd30 : inout bit; la15_rc30 : inout bit; la16_rd29 : inout bit; la17_rc29 : inout bit; la18_rd28 : inout bit; la19_rc28 : inout bit; la1_rc37 : inout bit; la2_rd36 : inout bit; la3_rc36 : inout bit; la4_rd35 : inout bit; la5_rc35 : inout bit; la6_rd34 : inout bit; la7_rc34 : inout bit; la8_rd33 : inout bit; la9_rc33 : inout bit; ld0_tc28 : inout bit; ld10_tc33 : inout bit; ld11_td33 : inout bit; ld12_tc34 : inout bit; ld13_td34 : inout bit; ld14_tc35 : inout bit; ld15_td35 : inout bit; ld1_td28 : inout bit; ld2_tc29 : inout bit; ld3_td29 : inout bit; ld4_tc30 : inout bit; ld5_td30 : inout bit; ld6_tc31 : inout bit; ld7_td31 : inout bit; ld8_tc32 : inout bit; ld9_td32 : inout bit; lint_tc37 : inout bit; lrd_rd38 : inout bit; lwr_rc39 : inout bit; pdevsel : inout bit; pframe : inout bit; pirdy : inout bit; ppar : inout bit; pperr : inout bit; pstop : inout bit; ptrdy : inout bit; pad : inout bit_vector (0 to 31); pcbe : inout bit_vector (0 to 3); jtdo : out bit; lbgack_td38 : out bit; lbhe_td37 : out bit; lclk_td36 : out bit; lhold_td39 : out bit; pinta : out bit; preq : out bit; pserr : out bit; pxas : out bit; pxblast : out bit; pxds : out bit; td : out bit_vector (0 to 27); VDD : linkage bit_vector (1 to 16); VSS : linkage bit_vector (1 to 17) ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of ds3131_top: entity is "STD_1149_1_1993"; attribute PIN_MAP of ds3131_top: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information -- is extracted from the port-to-pin map file that was read in using -- the "read_pin_map" command. constant PBGA_256: PIN_MAP_STRING := "jtclk : B18," & "jtdi : C17," & "jtms : A19," & "jtrst : B17," & "lbpxs : B9," & "lcs_rc38 : B8," & "lhlda_tc38 : C11," & "lim_tc36 : C12," & "lms_rd39 : C9," & "lrdy_tc39 : A10," & "pclk : Y2," & "pgnt : W4," & "pidsel : Y6," & "prst : W3," & "sen_n : W9," & "smode_n : C10," & "testmode_n : Y19," & "rc : (Y1, V3, V2, T4, U2, U1, R3, T1, P3, P2, N3, N1, M2, " & "L3, L1, K3, J1, J3, H1, H3, G2, F1, G4, E1, E3, C1, D3, C2)," & "rd : (W2, W1, U3, V1, T3, T2, P4, R2, R1, P1, N2, M3, M1, " & "L2, K1, K2, J2, J4, H2, G1, G3, F2, F3, E2, D1, E4, D2, B1)," & "tc : (W20, U19, T17, U20, T19, R18, R19, P18, P20, N19, " & "M17, M19, L19, L20, K19, J20, J18, H19, G20, F20, F19, G17, E19, " & "E18, C20, D18, B20, B19)," & "la0_rd37 : C8," & "la10_rd32 : A4," & "la11_rc32 : C5," & "la12_rd31 : B4," & "la13_rc31 : A3," & "la14_rd30 : D5," & "la15_rc30 : C4," & "la16_rd29 : B3," & "la17_rc29 : B2," & "la18_rd28 : A2," & "la19_rc28 : C3," & "la1_rc37 : A7," & "la2_rd36 : B7," & "la3_rc36 : A6," & "la4_rd35 : C7," & "la5_rc35 : B6," & "la6_rd34 : A5," & "la7_rc34 : D7," & "la8_rd33 : C6," & "la9_rc33 : B5," & "ld0_tc28 : A18," & "ld10_tc33 : B14," & "ld11_td33 : A14," & "ld12_tc34 : C13," & "ld13_td34 : B13," & "ld14_tc35 : A13," & "ld15_td35 : D12," & "ld1_td28 : A17," & "ld2_tc29 : C16," & "ld3_td29 : B16," & "ld4_tc30 : A16," & "ld5_td30 : C15," & "ld6_tc31 : D14," & "ld7_td31 : B15," & "ld8_tc32 : A15," & "ld9_td32 : C14," & "lint_tc37 : A12," & "lrd_rd38 : A8," & "lwr_rc39 : A9," & "pdevsel : Y11," & "pframe : W10," & "pirdy : V10," & "ppar : W12," & "pperr : V11," & "pstop : W11," & "ptrdy : Y10," & "pad : (V17, U16, Y18, W17, V16, Y17, W16, V15, W15, V14, " & "Y15, W14, Y14, V13, W13, Y13, V9, U9, Y8, W8, V8, Y7, W7, V7, U7, " & "V6, Y5, W5, V5, Y4, Y3, U5)," & "pcbe : (Y16, V12, Y9, W6)," & "jtdo : D16," & "lbgack_td38 : A11," & "lbhe_td37 : B11," & "lclk_td36 : B12," & "lhold_td39 : B10," & "pinta : W18," & "preq : V4," & "pserr : Y12," & "pxas : V18," & "pxblast : Y20," & "pxds : W19," & "td : (V19, U18, V20, T18, T20, P17, R20, P19, N18, N20, " & "M18, M20, L18, K20, K18, J19, H20, H18, G19, G18, E20, F18, D20, " & "D19, E17, C19, C18, A20)," & "VDD : (D6, D10, D11, D15, F4, F17, K4, K17, L4, L17, R4, " & "R17, U6, U10, U11, U15)," & "VSS : (A1, D4, D8, D9, D13, D17, H4, H17, J17, M4, N4, N17" & ", U4, U8, U12, U13, U17)"; -- This section specifies the TAP ports. -- For the TAP TCK port, the parameters in the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of jtclk: signal is (10.0e6, BOTH); attribute TAP_SCAN_IN of jtdi : signal is true; attribute TAP_SCAN_MODE of jtms : signal is true; attribute TAP_SCAN_OUT of jtdo : signal is true; attribute TAP_SCAN_RESET of jtrst: signal is true; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of ds3131_top: entity is 3; -- Specifies the boundary-scan instructions implemented in the -- design and their opcodes. attribute INSTRUCTION_OPCODE of ds3131_top: entity is "BYPASS (111)," & "EXTEST (000)," & "SAMPLE (010)," & "CLAMP (011)," & "HIGHZ (100)," & "USER1 (101)," & "USER2 (110)," & "IDCODE (001)"; -- Specifies the bit pattern that is loaded into the instruction -- register when the TAP controller passes through the Capture-IR -- state. The standard mandates that the two LSBs must be "01". -- The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of ds3131_top: entity is "001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID -- register during the IDCODE instruction when the TAP controller -- passes through the Capture-DR state. attribute IDCODE_REGISTER of ds3131_top: entity is "0000" & -- 4-bit version number "0000000000001000" & -- 16-bit part number "00010100001" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 -- This section specifies the test data register placed between TDI -- and TDO for each implemented instruction. attribute REGISTER_ACCESS of ds3131_top: entity is "BYPASS (BYPASS, CLAMP, HIGHZ, USER1, USER2)," & "BOUNDARY (EXTEST, SAMPLE)," & "DEVICE_ID (IDCODE)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of ds3131_top: entity is 325; -- The following list specifies the characteristics of each cell -- in the boundary scan register from TDI to TDO. -- The following is a description of the label fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not -- have a port name. -- function: Is the function of the cell as defined by the -- standard. Is one of input, output2, output3, -- bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be -- loaded with for safe operation when the software -- might otherwise choose a random value. -- ccell : The control cell number. Specifies the control -- cell that drives the output enable for this port. -- disval : Specifies the value that is loaded into the -- control cell to disable the output enable for -- the corresponding port. -- rslt : Resulting state. Shows the state of the driver -- when it is disabled. attribute BOUNDARY_REGISTER of ds3131_top: entity is -- -- num cell port function safe [ccell disval rslt] -- "324 (BC_4, ld0_tc28, observe_only, X), " & "323 (BC_2, ld0_tc28, output3, X, 310, 1, Z), " & "322 (BC_4, ld1_td28, observe_only, X), " & "321 (BC_2, ld1_td28, output3, X, 307, 1, Z), " & "320 (BC_4, ld2_tc29, observe_only, X), " & "319 (BC_2, ld2_tc29, output3, X, 310, 1, Z), " & "318 (BC_4, ld3_td29, observe_only, X), " & "317 (BC_2, ld3_td29, output3, X, 307, 1, Z), " & "316 (BC_4, ld4_tc30, observe_only, X), " & "315 (BC_2, ld4_tc30, output3, X, 310, 1, Z), " & "314 (BC_4, ld5_td30, observe_only, X), " & "313 (BC_2, ld5_td30, output3, X, 307, 1, Z), " & "312 (BC_4, ld6_tc31, observe_only, X), " & "311 (BC_2, ld6_tc31, output3, X, 310, 1, Z), " & "310 (BC_2, *, controlr, 1), " & "309 (BC_4, ld7_td31, observe_only, X), " & "308 (BC_2, ld7_td31, output3, X, 307, 1, Z), " & "307 (BC_2, *, controlr, 1), " & "306 (BC_4, ld8_tc32, observe_only, X), " & "305 (BC_2, ld8_tc32, output3, X, 292, 1, Z), " & "304 (BC_4, ld9_td32, observe_only, X), " & "303 (BC_2, ld9_td32, output3, X, 289, 1, Z), " & "302 (BC_4, ld10_tc33, observe_only, X), " & "301 (BC_2, ld10_tc33, output3, X, 292, 1, Z), " & "300 (BC_4, ld11_td33, observe_only, X), " & "299 (BC_2, ld11_td33, output3, X, 289, 1, Z), " & "298 (BC_4, ld12_tc34, observe_only, X), " & "297 (BC_2, ld12_tc34, output3, X, 292, 1, Z), " & "296 (BC_4, ld13_td34, observe_only, X), " & "295 (BC_2, ld13_td34, output3, X, 289, 1, Z), " & "294 (BC_4, ld14_tc35, observe_only, X), " & "293 (BC_2, ld14_tc35, output3, X, 292, 1, Z), " & "292 (BC_2, *, controlr, 1), " & "291 (BC_4, ld15_td35, observe_only, X), " & "290 (BC_2, ld15_td35, output3, X, 289, 1, Z), " & "289 (BC_2, *, controlr, 1), " & "288 (BC_4, lim_tc36, observe_only, X), " & "287 (BC_2, lclk_td36, output3, X, 286, 1, Z), " & "286 (BC_2, *, controlr, 1), " & "285 (BC_4, lint_tc37, observe_only, X), " & "284 (BC_2, lint_tc37, output2, 1, 284, 1, weak1), " & "283 (BC_2, *, internal, 0), " & "282 (BC_2, lbhe_td37, output3, X, 281, 1, Z), " & "281 (BC_2, *, controlr, 1), " & "280 (BC_4, lhlda_tc38, observe_only, X), " & "279 (BC_2, lbgack_td38, output3, X, 278, 1, Z), " & "278 (BC_2, *, controlr, 1), " & "277 (BC_4, lrdy_tc39, observe_only, X), " & "276 (BC_2, lhold_td39, output3, X, 58, 1, Z), " & "275 (BC_4, lwr_rc39, observe_only, X), " & "274 (BC_2, lwr_rc39, output3, X, 273, 1, Z), " & "273 (BC_2, *, controlr, 1), " & "272 (BC_4, lbpxs, observe_only, X), " & "271 (BC_4, lms_rd39, observe_only, X), " & "270 (BC_4, lrd_rd38, observe_only, X), " & "269 (BC_2, lrd_rd38, output3, X, 268, 1, Z), " & "268 (BC_2, *, controlr, 1), " & "267 (BC_4, lcs_rc38, observe_only, X), " & "266 (BC_4, la0_rd37, observe_only, X), " & "265 (BC_2, la0_rd37, output3, X, 264, 1, Z), " & "264 (BC_2, *, controlr, 1), " & "263 (BC_4, la1_rc37, observe_only, X), " & "262 (BC_2, la1_rc37, output3, X, 264, 1, Z), " & "261 (BC_4, la2_rd36, observe_only, X), " & "260 (BC_2, la2_rd36, output3, X, 264, 1, Z), " & "259 (BC_4, la3_rc36, observe_only, X), " & "258 (BC_2, la3_rc36, output3, X, 264, 1, Z), " & "257 (BC_4, la4_rd35, observe_only, X), " & "256 (BC_2, la4_rd35, output3, X, 264, 1, Z), " & "255 (BC_4, la5_rc35, observe_only, X), " & "254 (BC_2, la5_rc35, output3, X, 264, 1, Z), " & "253 (BC_4, la6_rd34, observe_only, X), " & "252 (BC_2, la6_rd34, output3, X, 264, 1, Z), " & "251 (BC_4, la7_rc34, observe_only, X), " & "250 (BC_2, la7_rc34, output3, X, 264, 1, Z), " & "249 (BC_4, la8_rd33, observe_only, X), " & "248 (BC_2, la8_rd33, output3, X, 264, 1, Z), " & "247 (BC_4, la9_rc33, observe_only, X), " & "246 (BC_2, la9_rc33, output3, X, 264, 1, Z), " & "245 (BC_4, la10_rd32, observe_only, X), " & "244 (BC_2, la10_rd32, output3, X, 264, 1, Z), " & "243 (BC_4, la11_rc32, observe_only, X), " & "242 (BC_2, la11_rc32, output3, X, 264, 1, Z), " & "241 (BC_4, la12_rd31, observe_only, X), " & "240 (BC_2, la12_rd31, output3, X, 264, 1, Z), " & "239 (BC_4, la13_rc31, observe_only, X), " & "238 (BC_2, la13_rc31, output3, X, 264, 1, Z), " & "237 (BC_4, la14_rd30, observe_only, X), " & "236 (BC_2, la14_rd30, output3, X, 264, 1, Z), " & "235 (BC_4, la15_rc30, observe_only, X), " & "234 (BC_2, la15_rc30, output3, X, 264, 1, Z), " & "233 (BC_4, la16_rd29, observe_only, X), " & "232 (BC_2, la16_rd29, output3, X, 264, 1, Z), " & "231 (BC_4, la17_rc29, observe_only, X), " & "230 (BC_2, la17_rc29, output3, X, 264, 1, Z), " & "229 (BC_4, la18_rd28, observe_only, X), " & "228 (BC_2, la18_rd28, output3, X, 264, 1, Z), " & "227 (BC_4, la19_rc28, observe_only, X), " & "226 (BC_2, la19_rc28, output3, X, 264, 1, Z), " & "225 (BC_4, rd(27), observe_only, X), " & "224 (BC_4, rc(27), observe_only, X), " & "223 (BC_4, rd(26), observe_only, X), " & "222 (BC_4, rc(26), observe_only, X), " & "221 (BC_4, rd(25), observe_only, X), " & "220 (BC_4, rc(25), observe_only, X), " & "219 (BC_4, rd(24), observe_only, X), " & "218 (BC_4, rc(24), observe_only, X), " & "217 (BC_4, rd(23), observe_only, X), " & "216 (BC_4, rc(23), observe_only, X), " & "215 (BC_4, rd(22), observe_only, X), " & "214 (BC_4, rc(22), observe_only, X), " & "213 (BC_4, rd(21), observe_only, X), " & "212 (BC_4, rc(21), observe_only, X), " & "211 (BC_4, rd(20), observe_only, X), " & "210 (BC_4, rc(20), observe_only, X), " & "209 (BC_4, rd(19), observe_only, X), " & "208 (BC_4, rc(19), observe_only, X), " & "207 (BC_4, rd(18), observe_only, X), " & "206 (BC_4, rc(18), observe_only, X), " & "205 (BC_4, rd(17), observe_only, X), " & "204 (BC_4, rc(17), observe_only, X), " & "203 (BC_4, rd(16), observe_only, X), " & "202 (BC_4, rc(16), observe_only, X), " & "201 (BC_4, rd(15), observe_only, X), " & "200 (BC_4, rc(15), observe_only, X), " & "199 (BC_4, rd(14), observe_only, X), " & "198 (BC_4, rc(14), observe_only, X), " & "197 (BC_4, rd(13), observe_only, X), " & "196 (BC_4, rc(13), observe_only, X), " & "195 (BC_4, rd(12), observe_only, X), " & "194 (BC_4, rc(12), observe_only, X), " & "193 (BC_4, rd(11), observe_only, X), " & "192 (BC_4, rc(11), observe_only, X), " & "191 (BC_4, rd(10), observe_only, X), " & "190 (BC_4, rc(10), observe_only, X), " & "189 (BC_4, rd(9), observe_only, X), " & "188 (BC_4, rc(9), observe_only, X), " & "187 (BC_4, rd(8), observe_only, X), " & "186 (BC_4, rc(8), observe_only, X), " & "185 (BC_4, rd(7), observe_only, X), " & "184 (BC_4, rc(7), observe_only, X), " & "183 (BC_4, rd(6), observe_only, X), " & "182 (BC_4, rc(6), observe_only, X), " & "181 (BC_4, rd(5), observe_only, X), " & "180 (BC_4, rc(5), observe_only, X), " & "179 (BC_4, rd(4), observe_only, X), " & "178 (BC_4, rc(4), observe_only, X), " & "177 (BC_4, rd(3), observe_only, X), " & "176 (BC_4, rc(3), observe_only, X), " & "175 (BC_4, rd(2), observe_only, X), " & "174 (BC_4, rc(2), observe_only, X), " & "173 (BC_4, rd(1), observe_only, X), " & "172 (BC_4, rc(1), observe_only, X), " & "171 (BC_4, rd(0), observe_only, X), " & "170 (BC_4, rc(0), observe_only, X), " & "169 (BC_4, prst, observe_only, X), " & "168 (BC_4, pclk, observe_only, X), " & "167 (BC_4, pgnt, observe_only, X), " & "166 (BC_2, preq, output3, X, 165, 1, Z), " & "165 (BC_2, *, controlr, 1), " & "164 (BC_4, pad(31), observe_only, X), " & "163 (BC_2, pad(31), output3, X, 162, 1, Z), " & "162 (BC_2, *, controlr, 1), " & "161 (BC_4, pad(30), observe_only, X), " & "160 (BC_2, pad(30), output3, X, 162, 1, Z), " & "159 (BC_4, pad(29), observe_only, X), " & "158 (BC_2, pad(29), output3, X, 162, 1, Z), " & "157 (BC_4, pad(28), observe_only, X), " & "156 (BC_2, pad(28), output3, X, 162, 1, Z), " & "155 (BC_4, pad(27), observe_only, X), " & "154 (BC_2, pad(27), output3, X, 162, 1, Z), " & "153 (BC_4, pad(26), observe_only, X), " & "152 (BC_2, pad(26), output3, X, 162, 1, Z), " & "151 (BC_4, pad(25), observe_only, X), " & "150 (BC_2, pad(25), output3, X, 162, 1, Z), " & "149 (BC_4, pad(24), observe_only, X), " & "148 (BC_2, pad(24), output3, X, 162, 1, Z), " & "147 (BC_4, pcbe(3), observe_only, X), " & "146 (BC_2, pcbe(3), output3, X, 145, 1, Z), " & "145 (BC_2, *, controlr, 1), " & "144 (BC_4, pidsel, observe_only, X), " & "143 (BC_4, pad(23), observe_only, X), " & "142 (BC_2, pad(23), output3, X, 162, 1, Z), " & "141 (BC_4, pad(22), observe_only, X), " & "140 (BC_2, pad(22), output3, X, 162, 1, Z), " & "139 (BC_4, pad(21), observe_only, X), " & "138 (BC_2, pad(21), output3, X, 162, 1, Z), " & "137 (BC_4, pad(20), observe_only, X), " & "136 (BC_2, pad(20), output3, X, 162, 1, Z), " & "135 (BC_4, pad(19), observe_only, X), " & "134 (BC_2, pad(19), output3, X, 162, 1, Z), " & "133 (BC_4, pad(18), observe_only, X), " & "132 (BC_2, pad(18), output3, X, 162, 1, Z), " & "131 (BC_4, pad(17), observe_only, X), " & "130 (BC_2, pad(17), output3, X, 162, 1, Z), " & "129 (BC_4, pad(16), observe_only, X), " & "128 (BC_2, pad(16), output3, X, 162, 1, Z), " & "127 (BC_4, pcbe(2), observe_only, X), " & "126 (BC_2, pcbe(2), output3, X, 125, 1, Z), " & "125 (BC_2, *, controlr, 1), " & "124 (BC_4, pframe, observe_only, X), " & "123 (BC_2, pframe, output3, X, 122, 1, Z), " & "122 (BC_2, *, controlr, 1), " & "121 (BC_4, pirdy, observe_only, X), " & "120 (BC_2, pirdy, output3, X, 119, 1, Z), " & "119 (BC_2, *, controlr, 1), " & "118 (BC_4, ptrdy, observe_only, X), " & "117 (BC_2, ptrdy, output3, X, 116, 1, Z), " & "116 (BC_2, *, controlr, 1), " & "115 (BC_4, pdevsel, observe_only, X), " & "114 (BC_2, pdevsel, output3, X, 113, 1, Z), " & "113 (BC_2, *, controlr, 1), " & "112 (BC_4, pstop, observe_only, X), " & "111 (BC_2, pstop, output3, X, 110, 1, Z), " & "110 (BC_2, *, controlr, 1), " & "109 (BC_4, pperr, observe_only, X), " & "108 (BC_2, pperr, output3, X, 107, 1, Z), " & "107 (BC_2, *, controlr, 1), " & "106 (BC_0, *, internal, X), " & "105 (BC_2, pserr, output2, 1, 105, 1, weak1), " & "104 (BC_2, *, internal, 0), " & "103 (BC_4, ppar, observe_only, X), " & "102 (BC_2, ppar, output3, X, 101, 1, Z), " & "101 (BC_2, *, controlr, 1), " & "100 (BC_4, pcbe(1), observe_only, X), " & "99 (BC_2, pcbe(1), output3, X, 98, 1, Z), " & "98 (BC_2, *, controlr, 1), " & "97 (BC_4, pad(15), observe_only, X), " & "96 (BC_2, pad(15), output3, X, 162, 1, Z), " & "95 (BC_4, pad(14), observe_only, X), " & "94 (BC_2, pad(14), output3, X, 162, 1, Z), " & "93 (BC_4, pad(13), observe_only, X), " & "92 (BC_2, pad(13), output3, X, 162, 1, Z), " & "91 (BC_4, pad(12), observe_only, X), " & "90 (BC_2, pad(12), output3, X, 162, 1, Z), " & "89 (BC_4, pad(11), observe_only, X), " & "88 (BC_2, pad(11), output3, X, 162, 1, Z), " & "87 (BC_4, pad(10), observe_only, X), " & "86 (BC_2, pad(10), output3, X, 162, 1, Z), " & "85 (BC_4, pad(9), observe_only, X), " & "84 (BC_2, pad(9), output3, X, 162, 1, Z), " & "83 (BC_4, pad(8), observe_only, X), " & "82 (BC_2, pad(8), output3, X, 162, 1, Z), " & "81 (BC_4, pcbe(0), observe_only, X), " & "80 (BC_2, pcbe(0), output3, X, 79, 1, Z), " & "79 (BC_2, *, controlr, 1), " & "78 (BC_4, pad(7), observe_only, X), " & "77 (BC_2, pad(7), output3, X, 162, 1, Z), " & "76 (BC_4, pad(6), observe_only, X), " & "75 (BC_2, pad(6), output3, X, 162, 1, Z), " & "74 (BC_4, pad(5), observe_only, X), " & "73 (BC_2, pad(5), output3, X, 162, 1, Z), " & "72 (BC_4, pad(4), observe_only, X), " & "71 (BC_2, pad(4), output3, X, 162, 1, Z), " & "70 (BC_4, pad(3), observe_only, X), " & "69 (BC_2, pad(3), output3, X, 162, 1, Z), " & "68 (BC_4, pad(2), observe_only, X), " & "67 (BC_2, pad(2), output3, X, 162, 1, Z), " & "66 (BC_4, pad(1), observe_only, X), " & "65 (BC_2, pad(1), output3, X, 162, 1, Z), " & "64 (BC_4, pad(0), observe_only, X), " & "63 (BC_2, pad(0), output3, X, 162, 1, Z), " & "62 (BC_0, *, internal, X), " & "61 (BC_2, pinta, output2, 1, 61, 1, weak1), " & "60 (BC_2, *, internal, 0), " & "59 (BC_2, pxas, output3, X, 58, 1, Z), " & "58 (BC_2, *, controlr, 1), " & "57 (BC_2, pxds, output3, X, 58, 1, Z), " & "56 (BC_2, pxblast, output3, X, 58, 1, Z), " & "55 (BC_4, tc(0), observe_only, X), " & "54 (BC_2, td(0), output3, X, 58, 1, Z), " & "53 (BC_4, tc(1), observe_only, X), " & "52 (BC_2, td(1), output3, X, 58, 1, Z), " & "51 (BC_4, tc(2), observe_only, X), " & "50 (BC_2, td(2), output3, X, 58, 1, Z), " & "49 (BC_4, tc(3), observe_only, X), " & "48 (BC_2, td(3), output3, X, 58, 1, Z), " & "47 (BC_4, tc(4), observe_only, X), " & "46 (BC_2, td(4), output3, X, 58, 1, Z), " & "45 (BC_4, tc(5), observe_only, X), " & "44 (BC_2, td(5), output3, X, 58, 1, Z), " & "43 (BC_4, tc(6), observe_only, X), " & "42 (BC_2, td(6), output3, X, 58, 1, Z), " & "41 (BC_4, tc(7), observe_only, X), " & "40 (BC_2, td(7), output3, X, 58, 1, Z), " & "39 (BC_4, tc(8), observe_only, X), " & "38 (BC_2, td(8), output3, X, 58, 1, Z), " & "37 (BC_4, tc(9), observe_only, X), " & "36 (BC_2, td(9), output3, X, 58, 1, Z), " & "35 (BC_4, tc(10), observe_only, X), " & "34 (BC_2, td(10), output3, X, 58, 1, Z), " & "33 (BC_4, tc(11), observe_only, X), " & "32 (BC_2, td(11), output3, X, 58, 1, Z), " & "31 (BC_4, tc(12), observe_only, X), " & "30 (BC_2, td(12), output3, X, 58, 1, Z), " & "29 (BC_4, tc(13), observe_only, X), " & "28 (BC_2, td(13), output3, X, 58, 1, Z), " & "27 (BC_4, tc(14), observe_only, X), " & "26 (BC_2, td(14), output3, X, 58, 1, Z), " & "25 (BC_4, tc(15), observe_only, X), " & "24 (BC_2, td(15), output3, X, 58, 1, Z), " & "23 (BC_4, tc(16), observe_only, X), " & "22 (BC_2, td(16), output3, X, 58, 1, Z), " & "21 (BC_4, tc(17), observe_only, X), " & "20 (BC_2, td(17), output3, X, 58, 1, Z), " & "19 (BC_4, tc(18), observe_only, X), " & "18 (BC_2, td(18), output3, X, 58, 1, Z), " & "17 (BC_4, tc(19), observe_only, X), " & "16 (BC_2, td(19), output3, X, 58, 1, Z), " & "15 (BC_4, tc(20), observe_only, X), " & "14 (BC_2, td(20), output3, X, 58, 1, Z), " & "13 (BC_4, tc(21), observe_only, X), " & "12 (BC_2, td(21), output3, X, 58, 1, Z), " & "11 (BC_4, tc(22), observe_only, X), " & "10 (BC_2, td(22), output3, X, 58, 1, Z), " & "9 (BC_4, tc(23), observe_only, X), " & "8 (BC_2, td(23), output3, X, 58, 1, Z), " & "7 (BC_4, tc(24), observe_only, X), " & "6 (BC_2, td(24), output3, X, 58, 1, Z), " & "5 (BC_4, tc(25), observe_only, X), " & "4 (BC_2, td(25), output3, X, 58, 1, Z), " & "3 (BC_4, tc(26), observe_only, X), " & "2 (BC_2, td(26), output3, X, 58, 1, Z), " & "1 (BC_4, tc(27), observe_only, X), " & "0 (BC_2, td(27), output3, X, 58, 1, Z) "; end ds3131_top;