//----------------------------------------------------------------------- // ds31256_revB2_top_gat_bsdl.v //----------------------------------------------------------------------- // // this file is manually generated (see README_bsdl_ds31256). it is a // merging of two verilog files: // // 1. ds31256_revB2_top_gat_no_core.v (output of gen_netlist.tcl) // 2. ds31256_revB2_cell_lib.v (manually created models file) // //----------------------------------------------------------------------- //-------------------------------------------------------------------- //-- NOTE: The behaviour of the LINT, PINTA, and PSERR pins is incorrect //-- in the BSDL file. It represents these pins as being capable //-- of driving a 0 or 1, but they actually drive a 0 or Z. //-- Currently, we do not have a solution for this problem. //-- //-- Designer: Dawn Murphy //-- Company: Dallas Semiconductor / Maxim //-------------------------------------------------------------------- //----------------------------------------------------------------------- //beginning of ds31256_revB2_top_gat_no_core.v //----------------------------------------------------------------------- module bscan_buffer_cell ( CLK_DR_OUT, HI_Z_OUT, MODE_OUT, RST_JTAG_OUT, SCAN_OUT, SHIFT_DR_OUT, UPDATE_DR_OUT, CLK_DR_IN, HI_Z_IN, MODE_IN, RST_JTAG_IN, SCAN_IN, SHIFT_DR_IN, UPDATE_DR_IN ); input CLK_DR_IN, HI_Z_IN, MODE_IN, RST_JTAG_IN, SCAN_IN, SHIFT_DR_IN, UPDATE_DR_IN; output CLK_DR_OUT, HI_Z_OUT, MODE_OUT, RST_JTAG_OUT, SCAN_OUT, SHIFT_DR_OUT, UPDATE_DR_OUT; wire scan_net_4, shift_dr_net_4, shift_dr_net_3, clk_dr_net_2, update_dr_net_4, scan_net_3, rst_jtag_net_2, update_dr_net_2, update_dr_net_3, shift_dr_net_2, scan_net_2, rst_jtag_net_3, rst_jtag_net_4, hi_z_net_2, mode_net_2, clk_dr_net_3, clk_dr_net_4, hi_z_net_3, mode_net_4, hi_z_net_4, mode_net_3; i1s1lu clk_dr_buf1 ( .IN(CLK_DR_IN), .OUT(clk_dr_net_2) ); i1s9lu update_dr_buf4 ( .IN(update_dr_net_4), .OUT(UPDATE_DR_OUT) ); i1s1lu hi_z_buf1 ( .IN(HI_Z_IN), .OUT(hi_z_net_2) ); i1s1lu scan_buf3 ( .IN(scan_net_3), .OUT(scan_net_4) ); i1s9lu shift_dr_buf4 ( .IN(shift_dr_net_4), .OUT(SHIFT_DR_OUT) ); i1s1lu rst_jtag_buf1 ( .IN(RST_JTAG_IN), .OUT(rst_jtag_net_2) ); i1s2lu scan_buf4 ( .IN(scan_net_4), .OUT(SCAN_OUT) ); i1s7lu shift_dr_buf3 ( .IN(shift_dr_net_3), .OUT(shift_dr_net_4) ); i1s7lu update_dr_buf3 ( .IN(update_dr_net_3), .OUT(update_dr_net_4) ); i1s1lu mode_buf1 ( .IN(MODE_IN), .OUT(mode_net_2) ); i1s3lu shift_dr_buf2 ( .IN(shift_dr_net_2), .OUT(shift_dr_net_3) ); i1s1lu scan_buf2 ( .IN(scan_net_2), .OUT(scan_net_3) ); i1s3lu update_dr_buf2 ( .IN(update_dr_net_2), .OUT(update_dr_net_3) ); i1s3lu clk_dr_buf2 ( .IN(clk_dr_net_2), .OUT(clk_dr_net_3) ); i1s7lu clk_dr_buf3 ( .IN(clk_dr_net_3), .OUT(clk_dr_net_4) ); i1s9lu clk_dr_buf4 ( .IN(clk_dr_net_4), .OUT(CLK_DR_OUT) ); i1s3lu hi_z_buf2 ( .IN(hi_z_net_2), .OUT(hi_z_net_3) ); i1s9lu mode_buf4 ( .IN(mode_net_4), .OUT(MODE_OUT) ); i1s9lu hi_z_buf4 ( .IN(hi_z_net_4), .OUT(HI_Z_OUT) ); i1s7lu mode_buf3 ( .IN(mode_net_3), .OUT(mode_net_4) ); i1s3lu rst_jtag_buf2 ( .IN(rst_jtag_net_2), .OUT(rst_jtag_net_3) ); i1s1lu shift_dr_buf1 ( .IN(SHIFT_DR_IN), .OUT(shift_dr_net_2) ); i1s3lu mode_buf2 ( .IN(mode_net_2), .OUT(mode_net_3) ); i1s7lu rst_jtag_buf3 ( .IN(rst_jtag_net_3), .OUT(rst_jtag_net_4) ); i1s1lu update_dr_buf1 ( .IN(UPDATE_DR_IN), .OUT(update_dr_net_2) ); i1s7lu hi_z_buf3 ( .IN(hi_z_net_3), .OUT(hi_z_net_4) ); i1s9lu rst_jtag_buf4 ( .IN(rst_jtag_net_4), .OUT(RST_JTAG_OUT) ); i1s1lu scan_buf1 ( .IN(SCAN_IN), .OUT(scan_net_2) ); endmodule module ipb_ph_vs_all ( GNDCORE ); input GNDCORE; endmodule module ipb_ph_vd_all ( VDDCORE ); input VDDCORE; endmodule module bscan_cntl_cell ( SCAN_IN, SYS_LOGIC_CNTL, CLOCKDR, UPDATEDR, SHIFTDR, RESET, SCAN_OUT, DIR_CNTL ); input SCAN_IN, SYS_LOGIC_CNTL, CLOCKDR, UPDATEDR, SHIFTDR, RESET; output SCAN_OUT, DIR_CNTL; wire Scan_out_delay, n109, Scan_in_delay, n100, _cell_7_net45, n107, n106, manual_eco_net1, manual_eco_net2, n111, n108, Scan_in_delayb, Sys_logic_cntl_delay, n110, Scan_out_delayb; dffacqs1lu Dir_cntl_reg ( .DIN(Scan_out_delay), .CLRB(n107), .CLK(UPDATEDR ), .OUT(manual_eco_net1) ); nor2s1lu U41 ( .IN1(n110), .IN2(SHIFTDR), .OUT(n109) ); ib1s6lu manual_eco_buf2 ( .IN(manual_eco_net2), .OUT(DIR_CNTL) ); dln1d3lu Scan_out_del ( .IN(SCAN_OUT), .OUT(Scan_out_delayb) ); oai21s3lu U40 ( .IN1(n111), .IN2(Scan_in_delay), .IN3(n106), .OUT(n108) ); dln1d3lu Scan_out_delb ( .IN(Scan_out_delayb), .OUT(Scan_out_delay) ); dln1d3lu scan_in_del ( .IN(SCAN_IN), .OUT(Scan_in_delayb) ); dln1d3lu Sys_logic_cntl_del ( .IN(SYS_LOGIC_CNTL), .OUT( Sys_logic_cntl_delay) ); ib1s2lu U39 ( .IN(n108), .OUT(n100) ); dffacqs1lu Scan_out_reg ( .DIN(n100), .CLRB(1'b1), .CLK(CLOCKDR), .OUT( SCAN_OUT) ); i1s1lu U37 ( .IN(_cell_7_net45), .OUT(n107) ); i1s1lu U42 ( .IN(SHIFTDR), .OUT(n111) ); ib1s3lu manual_eco_buf1 ( .IN(manual_eco_net1), .OUT(manual_eco_net2) ); dln1d3lu scan_in_5delb ( .IN(Scan_in_delayb), .OUT(Scan_in_delay) ); nor2s1lu U36 ( .IN1(_cell_7_net45), .IN2(n109), .OUT(n106) ); i1s1lu U43 ( .IN(Sys_logic_cntl_delay), .OUT(n110) ); i1s1lu U38 ( .IN(RESET), .OUT(_cell_7_net45) ); endmodule module core ( LD_OUT_AH, LD_ENHI_AZ, LD_ENLO_AZ, LA_OUT_RH, LA_EN_RZ, LWR_OUT_RZ, LWR_EN_RZ, LRD_OUT_RZ, LRD_EN_RZ, LBHE_RZ, LBHE_EN_RZ, LHOLD_RH, LBGACK_RZ, LMS_AZ, LCLKE_RZ, LINT_OUT_RZ, LD_IN_AH, LA_IN_AH, LWR_IN_AZ, LRD_IN_AZ, LIM_AH, LMS_AH, LRDY_AZ, LCS_AZ, LHLDA_AH, LINT_IN_AZ, PCI_AD_OUT, PCI_CBE_OUT_L, PCI_FRAME_OUT_L, PCI_IRDY_OUT_L, PCI_TRDY_OUT_L, PCI_STOP_OUT_L, PCI_DEVSEL_OUT_L, PCI_PAR_OUT, PCI_PERR_OUT_L, PCIX_ADS_L, PCIX_DS_L, PCIX_BLAST_L, PCI_SERR_L, PCI_REQ_L, PCI_FRAME_EN_L, PCI_IRDY_EN_L, PCI_CBE_EN_L, PCI_AD_EN_L, PCI_PAR_EN_L, PCI_TRGT_EN_L, PCI_PERR_EN_L, PCI_AD_IN, PCI_CBE_IN_L, PCI_FRAME_IN_L, PCI_IRDY_IN_L, PCI_TRDY_IN_L, PCI_STOP_IN_L, PCI_DEVSEL_IN_L, PCI_PAR_IN, PCI_PERR_IN_L, PCI_GNT_L, PCI_IDSEL, PCI_CLK, PCI_RST, PCI_RSTZ, PCI_66MHZ_CAPABLE_AH, SYSCLK_C, TD_AH, RC_AH, RD_AH, RS_AH, TC_AH, TS_AH ); output [15:0] LD_OUT_AH; output [19:0] LA_OUT_RH; input [3:0] PCI_CBE_IN_L; input [15:0] TC_AH; input [19:0] LA_IN_AH; input [15:0] LD_IN_AH; input [31:0] PCI_AD_IN; input [15:0] RC_AH; output [31:0] PCI_AD_OUT; output [3:0] PCI_CBE_OUT_L; output [15:0] TD_AH; input [15:0] TS_AH; input [15:0] RD_AH; input [15:0] RS_AH; input LWR_IN_AZ, LRD_IN_AZ, LIM_AH, LMS_AH, LRDY_AZ, LCS_AZ, LHLDA_AH, LINT_IN_AZ, PCI_FRAME_IN_L, PCI_IRDY_IN_L, PCI_TRDY_IN_L, PCI_STOP_IN_L, PCI_DEVSEL_IN_L, PCI_PAR_IN, PCI_PERR_IN_L, PCI_GNT_L, PCI_IDSEL, PCI_CLK, PCI_RST, PCI_66MHZ_CAPABLE_AH; output LD_ENHI_AZ, LD_ENLO_AZ, LA_EN_RZ, LWR_OUT_RZ, LWR_EN_RZ, LRD_OUT_RZ, LRD_EN_RZ, LBHE_RZ, LBHE_EN_RZ, LHOLD_RH, LBGACK_RZ, LMS_AZ, LCLKE_RZ, LINT_OUT_RZ, PCI_FRAME_OUT_L, PCI_IRDY_OUT_L, PCI_TRDY_OUT_L, PCI_STOP_OUT_L, PCI_DEVSEL_OUT_L, PCI_PAR_OUT, PCI_PERR_OUT_L, PCIX_ADS_L, PCIX_DS_L, PCIX_BLAST_L, PCI_SERR_L, PCI_REQ_L, PCI_FRAME_EN_L, PCI_IRDY_EN_L, PCI_CBE_EN_L, PCI_AD_EN_L, PCI_PAR_EN_L, PCI_TRGT_EN_L, PCI_PERR_EN_L, PCI_RSTZ, SYSCLK_C; wire NOT_PCI_RST, NOT_LMS_AH; assign LD_OUT_AH[15] = 1'b0; assign LD_OUT_AH[14] = 1'b0; assign LD_OUT_AH[13] = 1'b0; assign LD_OUT_AH[12] = 1'b0; assign LD_OUT_AH[11] = 1'b0; assign LD_OUT_AH[10] = 1'b0; assign LD_OUT_AH[9] = 1'b0; assign LD_OUT_AH[8] = 1'b0; assign LD_OUT_AH[7] = 1'b0; assign LD_OUT_AH[6] = 1'b0; assign LD_OUT_AH[5] = 1'b0; assign LD_OUT_AH[4] = 1'b0; assign LD_OUT_AH[3] = 1'b0; assign LD_OUT_AH[2] = 1'b0; assign LD_OUT_AH[1] = 1'b0; assign LD_OUT_AH[0] = 1'b0; assign LD_ENHI_AZ = 1'b1; assign LD_ENLO_AZ = 1'b1; assign LA_OUT_RH[19] = 1'b0; assign LA_OUT_RH[18] = 1'b0; assign LA_OUT_RH[17] = 1'b0; assign LA_OUT_RH[16] = 1'b0; assign LA_OUT_RH[15] = 1'b0; assign LA_OUT_RH[14] = 1'b0; assign LA_OUT_RH[13] = 1'b0; assign LA_OUT_RH[12] = 1'b0; assign LA_OUT_RH[11] = 1'b0; assign LA_OUT_RH[10] = 1'b0; assign LA_OUT_RH[9] = 1'b0; assign LA_OUT_RH[8] = 1'b0; assign LA_OUT_RH[7] = 1'b0; assign LA_OUT_RH[6] = 1'b0; assign LA_OUT_RH[5] = 1'b0; assign LA_OUT_RH[4] = 1'b0; assign LA_OUT_RH[3] = 1'b0; assign LA_OUT_RH[2] = 1'b0; assign LA_OUT_RH[1] = 1'b0; assign LA_OUT_RH[0] = 1'b0; assign LWR_OUT_RZ = 1'b1; assign LWR_EN_RZ = 1'b1; assign LRD_OUT_RZ = 1'b1; assign LRD_EN_RZ = 1'b1; assign LBHE_RZ = 1'b1; assign LBHE_EN_RZ = 1'b1; assign LHOLD_RH = 1'b0; assign LBGACK_RZ = 1'b1; assign LCLKE_RZ = 1'b1; assign LINT_OUT_RZ = 1'b1; assign PCI_AD_OUT[31] = 1'b0; assign PCI_AD_OUT[30] = 1'b0; assign PCI_AD_OUT[29] = 1'b0; assign PCI_AD_OUT[28] = 1'b0; assign PCI_AD_OUT[27] = 1'b0; assign PCI_AD_OUT[26] = 1'b0; assign PCI_AD_OUT[25] = 1'b0; assign PCI_AD_OUT[24] = 1'b0; assign PCI_AD_OUT[23] = 1'b0; assign PCI_AD_OUT[22] = 1'b0; assign PCI_AD_OUT[21] = 1'b0; assign PCI_AD_OUT[20] = 1'b0; assign PCI_AD_OUT[19] = 1'b0; assign PCI_AD_OUT[18] = 1'b0; assign PCI_AD_OUT[17] = 1'b0; assign PCI_AD_OUT[16] = 1'b0; assign PCI_AD_OUT[15] = 1'b0; assign PCI_AD_OUT[14] = 1'b0; assign PCI_AD_OUT[13] = 1'b0; assign PCI_AD_OUT[12] = 1'b0; assign PCI_AD_OUT[11] = 1'b0; assign PCI_AD_OUT[10] = 1'b0; assign PCI_AD_OUT[9] = 1'b0; assign PCI_AD_OUT[8] = 1'b0; assign PCI_AD_OUT[7] = 1'b0; assign PCI_AD_OUT[6] = 1'b0; assign PCI_AD_OUT[5] = 1'b0; assign PCI_AD_OUT[4] = 1'b0; assign PCI_AD_OUT[3] = 1'b0; assign PCI_AD_OUT[2] = 1'b0; assign PCI_AD_OUT[1] = 1'b0; assign PCI_AD_OUT[0] = 1'b0; assign PCI_CBE_OUT_L[3] = 1'b0; assign PCI_CBE_OUT_L[2] = 1'b0; assign PCI_CBE_OUT_L[1] = 1'b0; assign PCI_CBE_OUT_L[0] = 1'b0; assign PCI_FRAME_OUT_L = 1'b1; assign PCI_IRDY_OUT_L = 1'b1; assign PCI_TRDY_OUT_L = 1'b1; assign PCI_STOP_OUT_L = 1'b1; assign PCI_DEVSEL_OUT_L = 1'b1; assign PCI_PAR_OUT = 1'b0; assign PCI_PERR_OUT_L = 1'b1; assign PCIX_ADS_L = 1'b1; assign PCIX_DS_L = 1'b1; assign PCIX_BLAST_L = 1'b1; assign PCI_SERR_L = 1'b1; assign PCI_REQ_L = 1'b1; assign PCI_FRAME_EN_L = 1'b1; assign PCI_IRDY_EN_L = 1'b1; assign PCI_CBE_EN_L = 1'b1; assign PCI_AD_EN_L = 1'b1; assign PCI_PAR_EN_L = 1'b1; assign PCI_TRGT_EN_L = 1'b1; assign PCI_PERR_EN_L = 1'b1; assign TD_AH[15] = 1'b0; assign TD_AH[14] = 1'b0; assign TD_AH[13] = 1'b0; assign TD_AH[12] = 1'b0; assign TD_AH[11] = 1'b0; assign TD_AH[10] = 1'b0; assign TD_AH[9] = 1'b0; assign TD_AH[8] = 1'b0; assign TD_AH[7] = 1'b0; assign TD_AH[6] = 1'b0; assign TD_AH[5] = 1'b0; assign TD_AH[4] = 1'b0; assign TD_AH[3] = 1'b0; assign TD_AH[2] = 1'b0; assign TD_AH[1] = 1'b0; assign TD_AH[0] = 1'b0; assign NOT_PCI_RST = ~PCI_RST; assign LA_EN_RZ = (NOT_PCI_RST | LMS_AH); assign LMS_AZ = (NOT_PCI_RST | NOT_LMS_AH); assign NOT_PCI_RST = ~PCI_RST; assign NOT_LMS_AH = ~LMS_AH; endmodule module tap_controller ( TMS, TCK, TRST, RESET, SELECT, ENABLE, SHIFTIR, CLOCKIR, UPDATEIR, SHIFTDR, CLOCKDR, UPDATEDR ); input TMS, TCK, TRST; output RESET, SELECT, ENABLE, SHIFTIR, CLOCKIR, UPDATEIR, SHIFTDR, CLOCKDR, UPDATEDR; wire n317, n330, n345, \D[0] , manual_eco_net3, n339, n325, n273, \D[2] , n350, manual_eco_net4, n319, manual_eco_net2, n336, n351, n342, n337, n318, \Q[1] , n338, n331, n328, n333, n346, n354, \D[3] , n326, \Q[2] , \Q[0] , n321, n341, n353, n348, ResetD, n349, n352, n334, n327, n335, n340, \D[1] , manual_eco_net1, n347, n329; dffasqs1 Enable_reg ( .DIN(n317), .SETB(TRST), .CLK(n273), .OUT(ENABLE) ); dffasqs1 Q_reg_3_ ( .DIN(\D[3] ), .SETB(TRST), .CLK(TCK), .OUT( manual_eco_net4) ); dffasqs1 Q_reg_1_ ( .DIN(\D[1] ), .SETB(TRST), .CLK(TCK), .OUT( manual_eco_net2) ); nnd2s2 U113 ( .IN1(n326), .IN2(\Q[2] ), .OUT(n338) ); nnd2s1 U134 ( .IN1(\Q[2] ), .IN2(n336), .OUT(n341) ); i1s1 U141 ( .IN(n350), .OUT(\D[3] ) ); or2s1 U148 ( .IN1(\Q[1] ), .IN2(n349), .OUT(n330) ); i1s1 U153 ( .IN(\Q[0] ), .OUT(n354) ); nor2s1 U126 ( .IN1(n351), .IN2(n352), .OUT(n328) ); mx21s1 U121 ( .SIN(n321), .IN1(n341), .IN2(n327), .OUT(n353) ); and2s1 U154 ( .IN1(\Q[0] ), .IN2(n328), .OUT(n334) ); dln094d2 manual_eco_buf2 ( .IN(manual_eco_net2), .OUT(\Q[1] ) ); dffacqs1 ShiftIR_reg ( .DIN(n319), .CLRB(TRST), .CLK(n273), .OUT(SHIFTIR) ); i1s4 U109 ( .IN(TCK), .OUT(n273) ); i1s1 U114 ( .IN(SELECT), .OUT(n321) ); nor2s1 U133 ( .IN1(\Q[2] ), .IN2(n342), .OUT(n345) ); nnd3s1 U146 ( .IN1(\Q[0] ), .IN2(\Q[1] ), .IN3(n347), .OUT(ResetD) ); oai21s1 U115 ( .IN1(n349), .IN2(n334), .IN3(n335), .OUT(\D[0] ) ); i1s3 U120 ( .IN(\Q[0] ), .OUT(n342) ); dln094d2 manual_eco_buf3 ( .IN(manual_eco_net3), .OUT(\Q[2] ) ); i1s1 U129 ( .IN(n329), .OUT(n336) ); i1s1 U147 ( .IN(ResetD), .OUT(n352) ); nnd3s2 U110 ( .IN1(SELECT), .IN2(n273), .IN3(n329), .OUT(CLOCKIR) ); nnd3s2 U112 ( .IN1(n273), .IN2(n321), .IN3(n329), .OUT(CLOCKDR) ); nnd2s1 U140 ( .IN1(\Q[0] ), .IN2(\Q[2] ), .OUT(n333) ); dffacqs1 ShiftDR_reg ( .DIN(n318), .CLRB(TRST), .CLK(n273), .OUT(SHIFTDR) ); nor2s1 U135 ( .IN1(SELECT), .IN2(n317), .OUT(n318) ); or2s1 U149 ( .IN1(SELECT), .IN2(n342), .OUT(n331) ); nnd2s1 U137 ( .IN1(\Q[2] ), .IN2(SELECT), .OUT(n348) ); and2s1 U152 ( .IN1(\Q[1] ), .IN2(n354), .OUT(n329) ); dln094d2 manual_eco_buf4 ( .IN(manual_eco_net4), .OUT(SELECT) ); nnd2s1 U117 ( .IN1(n326), .IN2(\Q[0] ), .OUT(n337) ); i1s1 U119 ( .IN(\Q[1] ), .OUT(n326) ); i1s1 U142 ( .IN(n338), .OUT(n351) ); and2s1 U122 ( .IN1(n351), .IN2(n342), .OUT(n327) ); nnd2s2 U125 ( .IN1(n345), .IN2(n346), .OUT(n335) ); dln174d6 U150 ( .IN(n325), .OUT(RESET) ); nor2s1 U139 ( .IN1(n339), .IN2(n341), .OUT(n340) ); or2s1 U145 ( .IN1(\Q[2] ), .IN2(n336), .OUT(n317) ); dln094d2 manual_eco_buf1 ( .IN(manual_eco_net1), .OUT(\Q[0] ) ); nor2s1 U130 ( .IN1(n348), .IN2(n337), .OUT(UPDATEIR) ); mxi21s1 U138 ( .SIN(TMS), .IN1(n340), .IN2(n328), .OUT(\D[1] ) ); dffasqs1 Q_reg_2_ ( .DIN(\D[2] ), .SETB(TRST), .CLK(TCK), .OUT( manual_eco_net3) ); nor2s1 U123 ( .IN1(n338), .IN2(n331), .OUT(UPDATEDR) ); dffasqs1 Q_reg_0_ ( .DIN(\D[0] ), .SETB(TRST), .CLK(TCK), .OUT( manual_eco_net1) ); nnd3s1 U116 ( .IN1(n333), .IN2(n328), .IN3(n330), .OUT(\D[2] ) ); nnd2s1 U131 ( .IN1(\Q[1] ), .IN2(TMS), .OUT(n346) ); i1s1 U143 ( .IN(TMS), .OUT(n349) ); nor2s1 U144 ( .IN1(n321), .IN2(n317), .OUT(n319) ); dffacqs1 Reset_reg ( .DIN(ResetD), .CLRB(TRST), .CLK(n273), .OUT(n325) ); and2s1 U118 ( .IN1(n321), .IN2(n337), .OUT(n339) ); i1s1 U136 ( .IN(n348), .OUT(n347) ); aoi211s3 U151 ( .IN1(n351), .IN2(n349), .IN3(n352), .IN4(n353), .OUT(n350) ); endmodule module id_reg ( SCAN_IN, SHIFTDR, CLOCKDR, SCAN_OUT ); input SCAN_IN, SHIFTDR, CLOCKDR; output SCAN_OUT; wire \idreg_Q28[31] , \idreg_Q28[27] , \idreg_D[17] , \idreg_Q28[23] , \idreg_Q28[14] , \idreg_D[24] , \idreg_D[3] , \idreg_Q28[19] , \idreg_Q28[10] , \idreg_D[13] , \idreg_D[20] , \idreg_D[30] , \idreg_D[29] , \idreg_D[18] , \idreg_D[7] , n40, \idreg_D[5] , \idreg_Q28[30] , \idreg_Q28[29] , \idreg_Q28[28] , \idreg_Q28[25] , \idreg_Q28[21] , \idreg_D[11] , \idreg_Q28[12] , \idreg_D[22] , \idreg_D[1] , \idreg_Q28[24] , \idreg_Q28[16] , \idreg_D[15] , \idreg_D[8] , \idreg_Q28[9] , \idreg_Q28[8] , \idreg_Q28[7] , \idreg_Q28[3] , \idreg_D[26] , n41, \idreg_Q28[5] , \idreg_Q28[1] , \idreg_Q28[6] , \idreg_Q28[4] , \idreg_Q28[0] , \idreg_Q28[2] , \idreg_D[14] , \idreg_D[9] , \idreg_D[0] , n42, \idreg_Q28[17] , \idreg_D[27] , \idreg_Q28[26] , \idreg_Q28[22] , \idreg_Q28[20] , \idreg_D[19] , \idreg_D[4] , \idreg_Q28[13] , \idreg_D[10] , \idreg_D[23] , \idreg_D[12] , \idreg_Q28[18] , \idreg_Q28[11] , \idreg_D[21] , \idreg_D[28] , \idreg_D[6] , n39, \idreg_Q28[15] , \idreg_D[16] , \idreg_D[25] , \idreg_D[2] ; dffqs2 idreg_Q_reg_31_ ( .DIN(\idreg_Q28[31] ), .CLK(CLOCKDR), .OUT( \idreg_D[30] ) ); dffqs2 idreg_Q_reg_30_ ( .DIN(\idreg_Q28[30] ), .CLK(CLOCKDR), .OUT( \idreg_D[29] ) ); dffqs2 idreg_Q_reg_29_ ( .DIN(\idreg_Q28[29] ), .CLK(CLOCKDR), .OUT( \idreg_D[28] ) ); dffqs2 idreg_Q_reg_26_ ( .DIN(\idreg_Q28[26] ), .CLK(CLOCKDR), .OUT( \idreg_D[25] ) ); dffqs2 idreg_Q_reg_15_ ( .DIN(\idreg_Q28[15] ), .CLK(CLOCKDR), .OUT( \idreg_D[14] ) ); or2s1 U54 ( .IN1(\idreg_D[6] ), .IN2(n39), .OUT(\idreg_Q28[6] ) ); or2s1 U73 ( .IN1(\idreg_D[16] ), .IN2(n40), .OUT(\idreg_Q28[16] ) ); dffqs2 idreg_Q_reg_22_ ( .DIN(\idreg_Q28[22] ), .CLK(CLOCKDR), .OUT( \idreg_D[21] ) ); dffqs2 idreg_Q_reg_11_ ( .DIN(\idreg_Q28[11] ), .CLK(CLOCKDR), .OUT( \idreg_D[10] ) ); dffqs2 idreg_Q_reg_4_ ( .DIN(\idreg_Q28[4] ), .CLK(CLOCKDR), .OUT( \idreg_D[3] ) ); dffqs2 idreg_Q_reg_0_ ( .DIN(\idreg_Q28[0] ), .CLK(CLOCKDR), .OUT(SCAN_OUT ) ); and2s1 U68 ( .IN1(\idreg_D[23] ), .IN2(n42), .OUT(\idreg_Q28[23] ) ); dffqs2 idreg_Q_reg_9_ ( .DIN(\idreg_Q28[9] ), .CLK(CLOCKDR), .OUT( \idreg_D[8] ) ); and2s1 U46 ( .IN1(\idreg_D[26] ), .IN2(n41), .OUT(\idreg_Q28[26] ) ); or2s1 U61 ( .IN1(\idreg_D[13] ), .IN2(n40), .OUT(\idreg_Q28[13] ) ); dffqs2 idreg_Q_reg_18_ ( .DIN(\idreg_Q28[18] ), .CLK(CLOCKDR), .OUT( \idreg_D[17] ) ); and2s1 U66 ( .IN1(\idreg_D[21] ), .IN2(n42), .OUT(\idreg_Q28[21] ) ); dffqs2 idreg_Q_reg_25_ ( .DIN(\idreg_Q28[25] ), .CLK(CLOCKDR), .OUT( \idreg_D[24] ) ); dffqs2 idreg_Q_reg_24_ ( .DIN(\idreg_Q28[24] ), .CLK(CLOCKDR), .OUT( \idreg_D[23] ) ); dffqs2 idreg_Q_reg_20_ ( .DIN(\idreg_Q28[20] ), .CLK(CLOCKDR), .OUT( \idreg_D[19] ) ); dffqs2 idreg_Q_reg_13_ ( .DIN(\idreg_Q28[13] ), .CLK(CLOCKDR), .OUT( \idreg_D[12] ) ); dffqs2 idreg_Q_reg_6_ ( .DIN(\idreg_Q28[6] ), .CLK(CLOCKDR), .OUT( \idreg_D[5] ) ); dffqs2 idreg_Q_reg_2_ ( .DIN(\idreg_Q28[2] ), .CLK(CLOCKDR), .OUT( \idreg_D[1] ) ); or2s1 U48 ( .IN1(\idreg_D[0] ), .IN2(n40), .OUT(\idreg_Q28[0] ) ); dffqs2 idreg_Q_reg_17_ ( .DIN(\idreg_Q28[17] ), .CLK(CLOCKDR), .OUT( \idreg_D[16] ) ); and2s1 U53 ( .IN1(\idreg_D[5] ), .IN2(n41), .OUT(\idreg_Q28[5] ) ); and2s1 U74 ( .IN1(\idreg_D[17] ), .IN2(n42), .OUT(\idreg_Q28[17] ) ); dffqs2 idreg_Q_reg_7_ ( .DIN(\idreg_Q28[7] ), .CLK(CLOCKDR), .OUT( \idreg_D[6] ) ); and2s1 U45 ( .IN1(\idreg_D[25] ), .IN2(n42), .OUT(\idreg_Q28[25] ) ); and2s1 U47 ( .IN1(\idreg_D[27] ), .IN2(n42), .OUT(\idreg_Q28[27] ) ); or2s1 U49 ( .IN1(\idreg_D[1] ), .IN2(n39), .OUT(\idreg_Q28[1] ) ); and2s1 U52 ( .IN1(\idreg_D[4] ), .IN2(n41), .OUT(\idreg_Q28[4] ) ); and2s1 U67 ( .IN1(\idreg_D[22] ), .IN2(n41), .OUT(\idreg_Q28[22] ) ); and2s1 U75 ( .IN1(\idreg_D[18] ), .IN2(SHIFTDR), .OUT(\idreg_Q28[18] ) ); and2s1 U55 ( .IN1(\idreg_D[7] ), .IN2(n41), .OUT(\idreg_Q28[7] ) ); or2s1 U69 ( .IN1(\idreg_D[28] ), .IN2(n40), .OUT(\idreg_Q28[28] ) ); and2s1 U72 ( .IN1(SCAN_IN), .IN2(n41), .OUT(\idreg_Q28[31] ) ); and2s1 U60 ( .IN1(\idreg_D[12] ), .IN2(n42), .OUT(\idreg_Q28[12] ) ); and2s1 U57 ( .IN1(n42), .IN2(\idreg_D[9] ), .OUT(\idreg_Q28[9] ) ); and2s1 U70 ( .IN1(\idreg_D[29] ), .IN2(n42), .OUT(\idreg_Q28[29] ) ); and2s1 U50 ( .IN1(\idreg_D[2] ), .IN2(n41), .OUT(\idreg_Q28[2] ) ); and2s1 U59 ( .IN1(\idreg_D[11] ), .IN2(n42), .OUT(\idreg_Q28[11] ) ); and2s1 U62 ( .IN1(\idreg_D[14] ), .IN2(n42), .OUT(\idreg_Q28[14] ) ); and2s1 U65 ( .IN1(\idreg_D[20] ), .IN2(n41), .OUT(\idreg_Q28[20] ) ); s2cd1s1 U77 ( .IN(SHIFTDR), .OUT(n42), .OUTB(n40) ); and2s1 U58 ( .IN1(\idreg_D[10] ), .IN2(n42), .OUT(\idreg_Q28[10] ) ); dffqs2 idreg_Q_reg_16_ ( .DIN(\idreg_Q28[16] ), .CLK(CLOCKDR), .OUT( \idreg_D[15] ) ); and2s1 U64 ( .IN1(\idreg_D[19] ), .IN2(n42), .OUT(\idreg_Q28[19] ) ); and2s1 U51 ( .IN1(\idreg_D[3] ), .IN2(n41), .OUT(\idreg_Q28[3] ) ); s2cd1s1 U76 ( .IN(SHIFTDR), .OUT(n41), .OUTB(n39) ); dffqs2 idreg_Q_reg_28_ ( .DIN(\idreg_Q28[28] ), .CLK(CLOCKDR), .OUT( \idreg_D[27] ) ); dffqs2 idreg_Q_reg_27_ ( .DIN(\idreg_Q28[27] ), .CLK(CLOCKDR), .OUT( \idreg_D[26] ) ); dffqs2 idreg_Q_reg_23_ ( .DIN(\idreg_Q28[23] ), .CLK(CLOCKDR), .OUT( \idreg_D[22] ) ); dffqs2 idreg_Q_reg_21_ ( .DIN(\idreg_Q28[21] ), .CLK(CLOCKDR), .OUT( \idreg_D[20] ) ); dffqs2 idreg_Q_reg_12_ ( .DIN(\idreg_Q28[12] ), .CLK(CLOCKDR), .OUT( \idreg_D[11] ) ); dffqs2 idreg_Q_reg_10_ ( .DIN(\idreg_Q28[10] ), .CLK(CLOCKDR), .OUT( \idreg_D[9] ) ); dffqs2 idreg_Q_reg_3_ ( .DIN(\idreg_Q28[3] ), .CLK(CLOCKDR), .OUT( \idreg_D[2] ) ); dffqs2 idreg_Q_reg_1_ ( .DIN(\idreg_Q28[1] ), .CLK(CLOCKDR), .OUT( \idreg_D[0] ) ); dffqs2 idreg_Q_reg_19_ ( .DIN(\idreg_Q28[19] ), .CLK(CLOCKDR), .OUT( \idreg_D[18] ) ); dffqs2 idreg_Q_reg_14_ ( .DIN(\idreg_Q28[14] ), .CLK(CLOCKDR), .OUT( \idreg_D[13] ) ); dffqs2 idreg_Q_reg_8_ ( .DIN(\idreg_Q28[8] ), .CLK(CLOCKDR), .OUT( \idreg_D[7] ) ); and2s1 U44 ( .IN1(\idreg_D[24] ), .IN2(n41), .OUT(\idreg_Q28[24] ) ); or2s1 U56 ( .IN1(\idreg_D[8] ), .IN2(n39), .OUT(\idreg_Q28[8] ) ); and2s1 U71 ( .IN1(\idreg_D[30] ), .IN2(n41), .OUT(\idreg_Q28[30] ) ); or2s1 U63 ( .IN1(\idreg_D[15] ), .IN2(n40), .OUT(\idreg_Q28[15] ) ); dffqs2 idreg_Q_reg_5_ ( .DIN(\idreg_Q28[5] ), .CLK(CLOCKDR), .OUT( \idreg_D[4] ) ); endmodule module IR_cell_00_1 ( DATA_IN, SHIFTIR, CLOCKIR, UPDATEIR, RESET, DATA_OUT, INSTR_BIT ); input DATA_IN, SHIFTIR, CLOCKIR, UPDATEIR, RESET; output DATA_OUT, INSTR_BIT; wire Data_out43; dffacqs2 Instr_bit_reg ( .DIN(DATA_OUT), .CLRB(RESET), .CLK(UPDATEIR), .OUT(INSTR_BIT) ); dffqs2 Data_out_reg ( .DIN(Data_out43), .CLK(CLOCKIR), .OUT(DATA_OUT) ); and2s1 U22 ( .IN1(SHIFTIR), .IN2(DATA_IN), .OUT(Data_out43) ); endmodule module IR_cell_00_0 ( DATA_IN, SHIFTIR, CLOCKIR, UPDATEIR, RESET, DATA_OUT, INSTR_BIT ); input DATA_IN, SHIFTIR, CLOCKIR, UPDATEIR, RESET; output DATA_OUT, INSTR_BIT; wire Data_out43; dffacqs2 Instr_bit_reg ( .DIN(DATA_OUT), .CLRB(RESET), .CLK(UPDATEIR), .OUT(INSTR_BIT) ); dffqs2 Data_out_reg ( .DIN(Data_out43), .CLK(CLOCKIR), .OUT(DATA_OUT) ); and2s1 U22 ( .IN1(SHIFTIR), .IN2(DATA_IN), .OUT(Data_out43) ); endmodule module IR_cell_11 ( DATA_IN, SHIFTIR, CLOCKIR, UPDATEIR, RESET, DATA_OUT, INSTR_BIT ); input DATA_IN, SHIFTIR, CLOCKIR, UPDATEIR, RESET; output DATA_OUT, INSTR_BIT; wire Data_out43, n90; dffqs2 Data_out_reg ( .DIN(Data_out43), .CLK(CLOCKIR), .OUT(DATA_OUT) ); i1s1 U24 ( .IN(DATA_IN), .OUT(n90) ); dffasqs1 Instr_bit_reg ( .DIN(DATA_OUT), .SETB(RESET), .CLK(UPDATEIR), .OUT(INSTR_BIT) ); nnd2s2 U23 ( .IN1(SHIFTIR), .IN2(n90), .OUT(Data_out43) ); endmodule module instr_reg ( SCAN_IN, SHIFTIR, CLOCKIR, UPDATEIR, RESET, SCAN_OUT, INSTR ); output [2:0] INSTR; input SCAN_IN, SHIFTIR, CLOCKIR, UPDATEIR, RESET; output SCAN_OUT; wire D1_out, D2_out; IR_cell_00_1 U2 ( .DATA_IN(SCAN_IN), .SHIFTIR(SHIFTIR), .CLOCKIR(CLOCKIR), .UPDATEIR(UPDATEIR), .RESET(RESET), .DATA_OUT(D2_out), .INSTR_BIT( INSTR[2]) ); IR_cell_00_0 U1 ( .DATA_IN(D2_out), .SHIFTIR(SHIFTIR), .CLOCKIR(CLOCKIR), .UPDATEIR(UPDATEIR), .RESET(RESET), .DATA_OUT(D1_out), .INSTR_BIT( INSTR[1]) ); IR_cell_11 U0 ( .DATA_IN(D1_out), .SHIFTIR(SHIFTIR), .CLOCKIR(CLOCKIR), .UPDATEIR(UPDATEIR), .RESET(RESET), .DATA_OUT(SCAN_OUT), .INSTR_BIT( INSTR[0]) ); endmodule module bypass_reg ( SCAN_IN, SHIFTDR, CLOCKDR, SCAN_OUT ); input SCAN_IN, SHIFTDR, CLOCKDR; output SCAN_OUT; wire Scan_out28; dffqs2 Scan_out_reg ( .DIN(Scan_out28), .CLK(CLOCKDR), .OUT(SCAN_OUT) ); and2s1 U10 ( .IN1(SHIFTDR), .IN2(SCAN_IN), .OUT(Scan_out28) ); endmodule module instr_dec ( INSTR, MODE, HI_Z, DEV_ID, BYP ); input [2:0] INSTR; output MODE, HI_Z, DEV_ID, BYP; wire n64, n67, n60, n55, n56, n54, n63, n57, n58, n59, n62; i1s3 U38 ( .IN(n64), .OUT(n57) ); i1s11 U39 ( .IN(n67), .OUT(MODE) ); i1s1 U40 ( .IN(n56), .OUT(n58) ); i1s4 U41 ( .IN(INSTR[1]), .OUT(n56) ); i1s1 U46 ( .IN(n59), .OUT(n60) ); or2s1 U54 ( .IN1(n60), .IN2(n62), .OUT(n67) ); oai21s3 U48 ( .IN1(n55), .IN2(n56), .IN3(n59), .OUT(BYP) ); nor3s1 U53 ( .IN1(n64), .IN2(n58), .IN3(n60), .OUT(DEV_ID) ); i1s4 U47 ( .IN(INSTR[0]), .OUT(n55) ); hi1s1 U49 ( .IN(INSTR[0]), .OUT(n64) ); xor2s1 U52 ( .IN1(n57), .IN2(n58), .OUT(n62) ); i1s5 U42 ( .IN(INSTR[2]), .OUT(n59) ); and2s1 U45 ( .IN1(n63), .IN2(n60), .OUT(n54) ); i1s10 U43 ( .IN(n54), .OUT(HI_Z) ); nor2s1 U51 ( .IN1(n57), .IN2(n58), .OUT(n63) ); endmodule module jtag_top ( TMS, TCK, TDI, TRST, TDO, TDO_ENB, SHIFTDR, UPDATEDR, CLOCKDR, RESET, MODE, HI_Z, SO_BS ); input TMS, TCK, TDI, TRST, SO_BS; output TDO, TDO_ENB, SHIFTDR, UPDATEDR, CLOCKDR, RESET, MODE, HI_Z; wire ShiftIR, ClockIR, n112, ClockDR_, SO_IR, n127, n135, n140, n_7, n129, Select, n128, n133, n132, n126, Byp, n_6, \Instr[1] , n141, UpdateDR_, n134, \Instr[0] , n136, n131, UpdateIR_, Dev_id, SO_Id, n130, \Instr[2] , n138, SO_BP, n139, UpdateIR, n137; tap_controller U1 ( .TMS(TMS), .TCK(TCK), .TRST(n131), .RESET(RESET), .SELECT(Select), .ENABLE(n128), .SHIFTIR(ShiftIR), .CLOCKIR(ClockIR), .UPDATEIR(UpdateIR_), .SHIFTDR(n112), .CLOCKDR(ClockDR_), .UPDATEDR( UpdateDR_) ); id_reg U6 ( .SCAN_IN(TDI), .SHIFTDR(n112), .CLOCKDR(ClockDR_), .SCAN_OUT( SO_Id) ); nor3s1 U54 ( .IN1(n134), .IN2(Dev_id), .IN3(n133), .OUT(n_6) ); i1s1 U41 ( .IN(n133), .OUT(n130) ); i1s1 U46 ( .IN(SO_BP), .OUT(n137) ); instr_reg U2 ( .SCAN_IN(TDI), .SHIFTIR(ShiftIR), .CLOCKIR(ClockIR), .UPDATEIR(UpdateIR), .RESET(RESET), .SCAN_OUT(SO_IR), .INSTR({ \Instr[2] , \Instr[1] , \Instr[0] }) ); bypass_reg U5 ( .SCAN_IN(TDI), .SHIFTDR(n112), .CLOCKDR(ClockDR_), .SCAN_OUT(SO_BP) ); dffacqs1 TDO_reg ( .DIN(n126), .CLRB(n131), .CLK(n_7), .OUT(n127) ); nnd2s2 U40 ( .IN1(n130), .IN2(n112), .OUT(n129) ); i1s1 U48 ( .IN(n128), .OUT(n141) ); mxi21s2 U53 ( .SIN(n133), .IN1(n136), .IN2(n137), .OUT(n135) ); i1s1 U39 ( .IN(UpdateDR_), .OUT(n134) ); i1s1 U47 ( .IN(SO_IR), .OUT(n139) ); i1s1 U49 ( .IN(n127), .OUT(n140) ); hi1s1 U52 ( .IN(Byp), .OUT(n132) ); mxi21s2 U55 ( .SIN(Select), .IN1(n138), .IN2(n139), .OUT(n126) ); i1s11 U42 ( .IN(n129), .OUT(SHIFTDR) ); i1s11 U45 ( .IN(n140), .OUT(TDO) ); instr_dec U3 ( .INSTR({\Instr[2] , \Instr[1] , \Instr[0] }), .MODE(MODE), .HI_Z(HI_Z), .DEV_ID(Dev_id), .BYP(Byp) ); i1s4 U37 ( .IN(TCK), .OUT(n_7) ); and2s3 S_1 ( .IN1(UpdateIR_), .IN2(n_7), .OUT(UpdateIR) ); nb1s1 U50 ( .IN(TRST), .OUT(n131) ); and2s3 S_7 ( .IN1(n_6), .IN2(n_7), .OUT(UPDATEDR) ); i1s3 U38 ( .IN(n132), .OUT(n133) ); i1s3 U43 ( .IN(SO_BS), .OUT(n136) ); mxi21s2 U51 ( .SIN(Dev_id), .IN1(n135), .IN2(SO_Id), .OUT(n138) ); or2s2 S_10 ( .IN1(ClockDR_), .IN2(Byp), .OUT(CLOCKDR) ); i1s11 U44 ( .IN(n141), .OUT(TDO_ENB) ); endmodule module bscan_cell ( PAD_OUT, PAD_ENB, PAD_IN, CORE_OUT, CORE_ENBZ, CORE_IN, SCAN_OUT, SCAN_IN, SHIFTDR, CLOCKDR, UPDATEDR, MODE, DIR_CNTL, HI_Z ); input PAD_IN, CORE_ENBZ, CORE_IN, SCAN_IN, SHIFTDR, CLOCKDR, UPDATEDR, MODE, DIR_CNTL, HI_Z; output PAD_OUT, PAD_ENB, CORE_OUT, SCAN_OUT; wire n131, Scan_in_delay, n135, n129, n134, Scan_out_delay, n132, Scan_out82, _cell_2_net32, n133, n128, n121, n126, S2, n124, Scan_in_delayb, n123, n122, n130, Dir_cntl_delay, Scan_out_delayb, n125, manual_eco_net1; ib1s3lu U54 ( .IN(n131), .OUT(n134) ); dffqs2lu S2_reg ( .DIN(Scan_out_delay), .CLK(UPDATEDR), .OUT(S2) ); i1s1lu U33 ( .IN(PAD_IN), .OUT(n123) ); nb1s6lu U46 ( .IN(n122), .OUT(PAD_OUT) ); i1s1lu U34 ( .IN(S2), .OUT(n124) ); i1s1lu U48 ( .IN(CORE_ENBZ), .OUT(n135) ); oai21s3lu U53 ( .IN1(n132), .IN2(Dir_cntl_delay), .IN3(n128), .OUT(n131) ); dln1d3lu Scan_out_del ( .IN(SCAN_OUT), .OUT(Scan_out_delayb) ); i1s1lu U49 ( .IN(HI_Z), .OUT(_cell_2_net32) ); ib1s2lu U52 ( .IN(n129), .OUT(n130) ); dln1d3lu Scan_out_delb ( .IN(Scan_out_delayb), .OUT(Scan_out_delay) ); hi1s1lu U55 ( .IN(n130), .OUT(n132) ); ib1s2lu U32 ( .IN(Scan_in_delay), .OUT(n125) ); nb1s6lu U47 ( .IN(n121), .OUT(CORE_OUT) ); dln1d3lu scan_in_del ( .IN(manual_eco_net1), .OUT(Scan_in_delayb) ); dln1d3lu scan_in_delb ( .IN(Scan_in_delayb), .OUT(Scan_in_delay) ); dffqs2lu Scan_out_reg ( .DIN(Scan_out82), .CLK(CLOCKDR), .OUT(SCAN_OUT) ); mxi21s2lu U39 ( .IN1(n126), .IN2(n124), .SIN(n130), .OUT(n122) ); ib1s6lu U57 ( .IN(n134), .OUT(PAD_ENB) ); mxi21s2lu U45 ( .IN1(n123), .IN2(n125), .SIN(SHIFTDR), .OUT(Scan_out82) ); dln1d3lu manual_eco_buf1 ( .IN(SCAN_IN), .OUT(manual_eco_net1) ); dln1d3lu Dir_cntl_del ( .IN(DIR_CNTL), .OUT(Dir_cntl_delay) ); nor2s2lu U50 ( .IN1(n133), .IN2(_cell_2_net32), .OUT(n128) ); i1s3lu U51 ( .IN(MODE), .OUT(n129) ); i1s1lu U31 ( .IN(CORE_IN), .OUT(n126) ); mxi21s2lu U38 ( .IN1(n123), .IN2(n124), .SIN(n130), .OUT(n121) ); nor2s1lu U56 ( .IN1(n130), .IN2(n135), .OUT(n133) ); endmodule module ds31256_top ( RC, RD, RS, TC, TD, TS, LHOLD, LBGACK, LBHE, LCLK, LMS, LIM, LRDY, LHLDA, LCS, LD, LA, LWR, LRD, LINT, JTDO, JTCLK, JTDI, JTRST, JTMS, PREQ, PSERR, PINTA, PCLK, PRST, PIDSEL, PGNT, PAD, PCBE, PPAR, PFRAME, PIRDY, PTRDY, PSTOP, PDEVSEL, PPERR, PCI_66MHZ_CAPABLE, PXAS, PXDS, PXBLAST ); input [15:0] RC; output [15:0] TD; inout [15:0] LD; inout [3:0] PCBE; input [15:0] RD; input [15:0] RS; input [15:0] TC; inout [31:0] PAD; input [15:0] TS; inout [19:0] LA; input LMS, LIM, LRDY, LHLDA, LCS, JTCLK, JTDI, JTRST, JTMS, PCLK, PRST, PIDSEL, PGNT, PCI_66MHZ_CAPABLE; output LHOLD, LBGACK, LBHE, LCLK, JTDO, PREQ, PSERR, PINTA, PXAS, PXDS, PXBLAST; inout LWR, LRD, LINT, PPAR, PFRAME, PIRDY, PTRDY, PSTOP, PDEVSEL, PPERR; wire clk_dr_west, rst_jtag_north, pci_irdy_out_jtag, pad17_sout, pad200_en, pad101_sout, \rd_ah[0] , pad147_en, pad14_en, \ts_ah[12] , \pci_ad_out_jtag[6] , \rs_ah[1] , \pci_ad_out[31] , lwr_cntl_sout, \pci_ad_out[28] , \td_jtag_ah[6] , \ld_out_jtag[8] , pad205_sout, lbgack_jtag, \pci_ad_in[3] , \la_out_rh[10] , pad221_sout, lbhe_jtag, \ld_out_jtag[12] , \ld_out_jtag[1] , \la_out_jtag[7] , \ld_in_ah[13] , \ld_out_ah[2] , ptrdy_en_jtag, pad237_sout, \pci_ad_out[21] , \tc_ah[6] , \rs_ah[8] , \pci_ad_out[12] , pad228_sout, clk_dr_east, so_bs, pad213_sout, \pci_ad_out_jtag[26] , \la_out_rh[19] , jtclk_c, \pci_ad_out_jtag[15] , pad83_en, pad25_sout, \ld_out_ah[15] , lcs_az, \rd_ah[11] , \rd_ah[9] , ppar_cntl_sout, pad126_en, pad108_sout, pad117_sout, jtms_ah, pad75_en, pad188_en, update_dr_north, \pci_ad_out_jtag[2] , \pci_ad_in[7] , \la_out_jtag[3] , \pci_cbe_out_jtag[2] , pad109_en, \la_out_rh[14] , pperr_en_jtag, pad216_en, pci_irdy_en_l, pad151_en, \td_jtag_ah[2] , pad238_sout, pad203_sout, \pci_ad_out_jtag[22] , \pci_ad_out_jtag[18] , \rs_ah[5] , \tc_ah[12] , \rd_ah[4] , pad123_sout, pad118_sout, pad123_en, pad28_en, \ld_out_ah[11] , \rd_ah[15] , pad86_en, pad11_sout, pad107_sout, \td_jtag_ah[12] , pad142_en, pad111_sout, scan_in_south, pad23_sout, \pci_ad_out_jtag[11] , pci_par_in, pad18_sout, \ld_out_jtag[5] , \tc_ah[2] , pad168_en, pad95_en, pad215_sout, \pci_ad_out[25] , pci_cbe_en_l, \ld_out_ah[6] , lms_az, \pci_ad_out[16] , \ld_out_jtag[14] , \tc_ah[0] , \la_out_jtag[8] , pad100_sout, pad170_en, pad124_sout, \pci_ad_out[27] , pad186_en, \pci_ad_out[14] , \pci_ad_out_jtag[9] , \ld_out_jtag[7] , \ld_out_ah[4] , \ld_in_ah[15] , \td_jtag_ah[9] , \ld_out_ah[13] , \td_jtag_ah[10] , mode_jtag_south, pad128_en, pad220_sout, mode_jtag_west, \pci_ad_out_jtag[20] , pad102_en, pad204_sout, \pci_ad_out_jtag[13] , \tc_ah[10] , pci_trdy_in_l, VSS, \pci_ad_out_jtag[30] , \pci_ad_out_jtag[29] , pci_frame_in_l, \rd_ah[6] , pad212_sout, pad229_sout, pad236_sout, \ts_ah[14] , \pci_ad_in[5] , \tc_ah[9] , pcbe2_en_jtag, pci_devsel_out_l, pad42_en, \la_out_jtag[1] , \pci_cbe_out_jtag[0] , pad111_en, \la_out_rh[16] , pad116_sout, \pci_ad_out_jtag[0] , \td_jtag_ah[0] , pad109_sout, \pci_ad_out_jtag[24] , pad149_en, \rs_ah[7] , pad24_sout, \pci_ad_out_jtag[17] , lim_ah, \pci_ad_in[8] , \ld_out_jtag[10] , \ld_out_jtag[3] , \ld_out_ah[0] , lrdy_az, pci_idsel, pad239_sout, \td_jtag_ah[14] , pad190_en, pdevsel_cntl_sout, pad226_sout, \rd_ah[13] , \ld_in_ah[11] , pad10_sout, \pci_ad_out[23] , \pci_ad_out[10] , rst_jtag_east, clk_dr, pad106_sout, pad119_sout, \tc_ah[4] , pad122_sout, pad19_sout, \rs_ah[3] , \pci_ad_out[19] , pad22_sout, \td_jtag_ah[4] , rst_jtag_west, \ts_ah[10] , \pci_ad_out_jtag[4] , pad183_en, \ld_out_ah[9] , \la_out_rh[12] , lint_en_jtag, pad175_en, pad110_sout, \pci_ad_in[1] , pad6_en, pad88_en, \la_out_jtag[5] , ld_enhi_az, lbhe_rz, pci_clk_jtag, la_en_jtag, pad107_en, \rd_ah[2] , hiz_jtag_south, pad230_sout, pad214_sout, \rc_ah[12] , \rc_ah[2] , \pci_ad_in[20] , \tc_ah[14] , \la_out_rh[5] , \pci_ad_out[8] , pci_devsel_in_l, \td_ah[4] , pad169_sout, pad152_sout, pframe_en_jtag, \pci_ad_in[13] , pad44_sout, pci_66mhz_capable_ah, pad244_en, pad60_sout, pad171_en, mode_jtag, pirdy_en_jtag, pad190_sout, pad176_sout, pad22_en, pad86_sout, clk_dr_south, \pci_cbe_in_l[0] , \td_ah[15] , pci_ad_en_l, pci_stop_in_l, \ts_ah[5] , \la_out_jtag[11] , pci_par_out, pad187_en, pci_trdy_out_l, pci_stop_out_jtag, pad249_sout, \ts_ah[1] , \pci_ad_in[30] , pad110_en, \pci_ad_out[1] , pcix_ds_l, pci_rstz, \la_out_jtag[18] , pad1_sout, pad148_en, pad240_sout, pad160_sout, lint_cntl_sout, \pci_ad_in[29] , \ld_in_ah[6] , pad76_sout, \la_in_ah[16] , pad186_sout, pad199_sout, pad52_sout, \la_in_ah[5] , pad252_en, \pci_ad_in[24] , \la_in_ah[8] , pci_gnt_l, \td_ah[11] , \la_out_jtag[15] , pad170_sout, pad250_sout, pad80_sout, pad66_sout, pad196_sout, pad79_sout, \pci_ad_in[17] , \la_out_rh[1] , pad191_en, ld_cntl_sout, pad189_sout, pad42_sout, \rc_ah[14] , \rc_ah[6] , \ts_ah[8] , \ld_in_ah[2] , \la_in_ah[12] , \td_ah[0] , pad154_sout, \la_in_ah[1] , pad179_sout, pad142_sout, lrd_in_az, \pci_cbe_out_l[2] , pad106_en, pad54_sout, pci_serr_l, \td_ah[9] , pad180_sout, \rs_ah[12] , \la_out_rh[8] , mode_jtag_east, \pci_ad_out[5] , pad96_sout, lrd_out_rz, lwr_in_az, pad174_en, pad87_sout, pad177_sout, pad191_sout, pad61_sout, \rc_ah[4] , pci_perr_en_l, pad_en_jtag, pad45_sout, pad153_sout, pad98_sout, pad168_sout, \la_in_ah[10] , pad248_sout, \la_in_ah[3] , \ld_in_ah[0] , \pci_cbe_out_l[0] , pad9_sout, \rs_ah[10] , \pci_ad_out[7] , pad146_en, pci_req_l, pstop_cntl_sout, pad241_sout, hiz_jtag_west, scan_in_west, hiz_jtag_north, shift_dr_north, \rc_ah[10] , \rc_ah[0] , \pci_ad_in[26] , \la_out_rh[3] , \la_in_ah[19] , pad82_en, \pci_ad_in[15] , pad127_en, \ld_in_ah[9] , pad238_en, sysclk_c, pad74_en, pad189_en, \td_ah[2] , \la_out_jtag[17] , pcbe0_cntl_sout, pad198_sout, pad53_sout, \ts_ah[3] , \pci_ad_in[18] , la_en_rz, \td_ah[13] , pad68_sout, lwr_out_jtag, pad187_sout, pad77_sout, pcbe0_en_jtag, pad161_sout, \ld_in_ah[4] , \rs_ah[14] , pad251_sout, \pci_ad_out[3] , pci_frame_out_l, pad122_en, pad71_en, \la_in_ah[14] , \la_in_ah[7] , pad87_en, pad155_sout, pad108_en, pci_rst, pad43_sout, pad188_sout, pad78_sout, pad150_en, pad197_sout, pcbe1_cntl_sout, jtdi_ah, pad67_sout, \rc_ah[11] , \rc_ah[9] , pcix_blast_jtag, pad81_sout, pad169_en, pad94_en, pad171_sout, pad97_sout, \ts_ah[7] , \pci_cbe_in_l[2] , rst_jtag, pad71_sout, pad55_sout, \pci_ad_in[22] , pad88_sout, \la_out_jtag[13] , pad143_sout, pad178_sout, \td_ah[6] , pad62_en, \pci_ad_in[19] , \pci_ad_in[11] , \la_out_rh[7] , pad143_en, \ld_in_ah[5] , pad48_en, pad6_sout, pdevsel_en_jtag, pad247_sout, \rs_ah[15] , \pci_ad_out[2] , pad139_en, \la_in_ah[15] , \la_in_ah[6] , pframe_cntl_sout, pad26_sout, \rc_ah[8] , \rc_ah[1] , lint_out_jtag, pinta_out_jtag, jtrst_ah, pad234_sout, pad219_sout, \pci_cbe_in_l[3] , pad172_en, pad222_sout, \la_out_jtag[12] , lwr_en_jtag, pad206_sout, \ts_ah[6] , \pci_ad_in[23] , pcix_ads_l, pad79_en, pad184_en, \pci_ad_in[10] , \la_out_rh[6] , pad126_sout, \td_ah[7] , pad14_sout, pad102_sout, pad100_en, mode_jtag_north, \rc_ah[15] , \rc_ah[5] , lhlda_ah, lint_in_az, pad230_en, pad139_sout, lwr_en_rz, \la_in_ah[11] , \pci_cbe_out_l[1] , pad177_en, lrd_cntl_sout, pad216_sout, pad105_en, pad136_sout, pad56_en, \rs_ah[11] , lrd_en_rz, \la_in_ah[2] , pci_irdy_in_l, pad20_sout, \pci_ad_out[6] , lrd_en_jtag, shift_dr_west, \ts_ah[2] , \pci_ad_in[27] , \ld_in_ah[8] , \ld_in_ah[1] , update_dr, pad112_sout, \la_in_ah[18] , pad104_sout, pad164_en, pcbe3_en_jtag, pad12_sout, pci_serr_jtag, \la_out_rh[2] , \td_ah[3] , pad36_sout, pad192_en, \pci_ad_in[14] , pad120_sout, pad200_sout, \la_out_jtag[16] , \td_ah[12] , pad116_en, pad224_sout, update_dr_west, \rc_ah[7] , \ts_ah[9] , \ts_ah[0] , \la_out_jtag[14] , jtdo_ah, \pci_ad_in[25] , pad27_sout, update_dr_south, \la_in_ah[9] , \td_ah[10] , pad38_sout, pad235_sout, \td_ah[1] , pad81_en, pad77_en, \pci_ad_in[16] , \la_out_rh[0] , hiz_jtag_east, pad124_en, pad211_sout, \ld_in_ah[3] , \rs_ah[13] , \la_in_ah[13] , \pci_cbe_out_l[3] , pad207_sout, \la_in_ah[0] , \pci_ad_out[4] , pci_perr_out_jtag, \la_out_rh[9] , \td_ah[8] , pci_clk, scan_in_north, pad218_sout, pad138_sout, pad137_en, pci_frame_en_l, \pci_ad_in[21] , \la_out_rh[4] , pad92_en, pad127_sout, pad140_en, \pci_ad_in[12] , \pci_ad_out[9] , pad217_sout, lwr_out_rz, \td_ah[5] , pad118_en, pad233_sout, lms_ah, \td_ah[14] , pcix_ads_jtag, pad208_sout, \pci_cbe_in_l[1] , pad97_en, lrd_out_jtag, pad21_sout, pad137_sout, \rc_ah[13] , \ts_ah[4] , ptrdy_cntl_sout, \la_out_jtag[10] , \rc_ah[3] , pad121_sout, pad37_sout, \pci_ad_out_jtag[25] , \pci_ad_in[31] , \pci_ad_in[28] , \ld_in_ah[7] , \la_out_jtag[19] , pad153_en, pad13_sout, pad28_sout, pci_trgt_en_l, pad121_en, pad105_sout, pad225_sout, pad72_en, rst_jtag_south, \la_in_ah[17] , \pci_ad_out[0] , \la_in_ah[4] , pad84_en, pad179_en, pad51_sout, pad147_sout, \pci_ad_out_jtag[16] , \ld_out_jtag[11] , lclke_rz, pci_irdy_out_l, \rd_ah[12] , shift_dr_east, hiz_jtag, pad93_sout, pad158_sout, pad76_en, \td_jtag_ah[15] , pad185_sout, pad75_sout, \pci_ad_out[22] , pad157_en, pad2_sout, \ld_out_jtag[2] , \pci_ad_out[11] , \ld_in_ah[10] , \ld_out_ah[1] , pad243_sout, clk_dr_north, \pci_ad_out_jtag[5] , \pci_ad_in[9] , shift_dr_south, pci_req_jtag, pad136_en, \tc_ah[5] , pci_frame_out_jtag, \ld_out_ah[8] , \td_jtag_ah[5] , \ts_ah[11] , \pci_ad_in[0] , \rs_ah[2] , \pci_ad_out[18] , shift_dr, pad93_en, \la_out_jtag[4] , VDD, \la_out_rh[13] , pci_par_out_jtag, pad58_sout, preq_en, pad85_sout, pad175_sout, \tc_ah[15] , pad151_sout, \tc_ah[1] , \rd_ah[3] , pad47_sout, \la_out_jtag[9] , pcbe3_cntl_sout, ppar_en_jtag, lbgack_rz, \pci_ad_out_jtag[8] , pad96_en, \ld_out_jtag[15] , \ld_out_jtag[6] , \ld_out_ah[5] , \ld_in_ah[14] , \td_jtag_ah[8] , \pci_ad_out[26] , pad4_sout, \pci_ad_out[15] , \pci_ad_out_jtag[21] , pcbe2_cntl_sout, ld_enlo_az, \td_jtag_ah[11] , update_dr_east, pad141_en, pad48_sout, pad183_sout, pad73_sout, pad95_sout, \pci_ad_out_jtag[12] , pad141_sout, \ld_out_ah[12] , pad119_en, pad57_sout, \rd_ah[7] , pci_devsel_out_jtag, pad41_sout, pad120_en, pad157_sout, pad73_en, \ts_ah[15] , \pci_ad_out_jtag[31] , \tc_ah[11] , pad85_en, pad178_en, pad83_sout, pad148_sout, pad173_sout, pci_perr_out_l, pad195_sout, \pci_ad_out_jtag[28] , \la_out_rh[17] , lhold_jtag, pcbe1_en_jtag, pad65_sout, \pci_ad_in[4] , \tc_ah[8] , \la_out_jtag[0] , \pci_cbe_out_jtag[1] , \pci_ad_out_jtag[1] , \rs_ah[6] , \td_jtag_ah[1] , pad152_en, \pci_ad_in[6] , \la_out_rh[15] , pad74_sout, pad184_sout, pad112_en, pad162_sout, \la_out_jtag[2] , pad159_sout, pad92_sout, \pci_cbe_out_jtag[3] , \pci_ad_out_jtag[23] , \pci_ad_out_jtag[19] , \pci_ad_out_jtag[3] , \rs_ah[4] , lbhe_en_rz, pad146_sout, \td_jtag_ah[3] , \tc_ah[13] , \rd_ah[5] , pad138_en, pci_perr_in_l, jtdo_en, pad242_sout, pad160_en, pad3_sout, \rd_ah[14] , \td_jtag_ah[13] , pperr_cntl_sout, pad159_en, \pci_ad_out_jtag[10] , lint_out_rz, \tc_ah[3] , \ld_out_ah[10] , pcix_ds_jtag, pad173_en, pad101_en, pad46_sout, \ld_out_jtag[4] , pad150_sout, \ld_out_ah[7] , pad174_sout, pad84_sout, \pci_ad_out[24] , \pci_ad_out[17] , pad62_sout, pad78_en, pad185_en, pad192_sout, pad59_sout, pad104_en, pcix_blast_l, pad5_sout, pad244_sout, lhold_rh, pci_par_en_l, \rd_ah[1] , \td_jtag_ah[7] , pad56_sout, pad252_sout, \pci_ad_out_jtag[7] , \ld_out_jtag[9] , scan_in_east, pirdy_cntl_sout, pad180_en, \ts_ah[13] , \pci_ad_in[2] , \rs_ah[0] , \pci_ad_out[30] , \pci_ad_out[29] , pad140_sout, \la_out_jtag[6] , ld_enlo_jtag, pci_trdy_out_jtag, pad164_sout, pad94_sout, \la_out_rh[11] , pad176_en, pstop_en_jtag, pad72_sout, la_cntl_sout, \ld_out_jtag[13] , \rs_ah[9] , \ld_out_jtag[0] , \pci_ad_out[20] , \ld_out_ah[3] , \pci_ad_out[13] , pad172_sout, \ld_in_ah[12] , pci_stop_out_l, pad82_sout, pad149_sout, \pci_ad_out_jtag[27] , \tc_ah[7] , \la_out_rh[18] , pad_cntl_sout, pad208_en, pad117_en, pad40_sout, \ld_out_ah[14] , pad98_en, \pci_ad_out_jtag[14] , \rd_ah[10] , \rd_ah[8] , pad222_en; bscan_buffer_cell bscan_buffer_cell_west ( .CLK_DR_OUT(clk_dr_west), .HI_Z_OUT(hiz_jtag_west), .MODE_OUT(mode_jtag_west), .RST_JTAG_OUT( rst_jtag_west), .SCAN_OUT(scan_in_west), .SHIFT_DR_OUT(shift_dr_west), .UPDATE_DR_OUT(update_dr_west), .CLK_DR_IN(clk_dr_north), .HI_Z_IN( hiz_jtag_north), .MODE_IN(mode_jtag_north), .RST_JTAG_IN( rst_jtag_north), .SCAN_IN(pad252_sout), .SHIFT_DR_IN(shift_dr_north), .UPDATE_DR_IN(update_dr_north) ); ipb_ph_in_5t_s pad1 ( .PADPIN(RC[0]), .Y(\rc_ah[0] ) ); ipb_ph_vs_all pad8 ( .GNDCORE(VSS) ); ipb_ph_in_5t_s pad27 ( .PADPIN(TS[3]), .Y(\ts_ah[3] ) ); ipb_ph_vd_all pad49 ( .VDDCORE(VDD) ); ipb_ph_in_5t_s pad158 ( .PADPIN(LHLDA), .Y(lhlda_ah) ); bscan_cell pad206_jtag ( .PAD_IN(\tc_ah[9] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad206_sout), .SCAN_IN(pad205_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cell pad219_jtag ( .PAD_IN(\rd_ah[11] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad219_sout), .SCAN_IN(pad218_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cell pad222_jtag ( .PAD_OUT(\td_jtag_ah[11] ), .PAD_ENB(pad222_en), .PAD_IN(\td_jtag_ah[11] ), .CORE_ENBZ(1'b0), .CORE_IN(\td_ah[11] ), .SCAN_OUT(pad222_sout), .SCAN_IN(pad221_sout), .SHIFTDR(shift_dr_north ), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE( mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cell pad14_jtag ( .PAD_OUT(\td_jtag_ah[1] ), .PAD_ENB(pad14_en), .PAD_IN(\td_jtag_ah[1] ), .CORE_ENBZ(1'b0), .CORE_IN(\td_ah[1] ), .SCAN_OUT(pad14_sout), .SCAN_IN(pad13_sout), .SHIFTDR(shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west ), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad102_jtag ( .PAD_OUT(\pci_cbe_out_jtag[1] ), .PAD_ENB( pad102_en), .PAD_IN(\pci_cbe_in_l[1] ), .CORE_ENBZ(pci_cbe_en_l), .CORE_IN(\pci_cbe_out_l[1] ), .SCAN_OUT(pad102_sout), .SCAN_IN( pcbe1_cntl_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL( pcbe1_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_vs_all pad90 ( .GNDCORE(VSS) ); ipb_ph_bi_08_5t_s pad111 ( .ENB(pad111_en), .IN0(\pci_ad_out_jtag[8] ), .Y(\pci_ad_in[8] ), .PADPIN(PAD[8]) ); ipb_ph_bi_04_5t_s pad136 ( .ENB(pad136_en), .IN0(\ld_out_jtag[0] ), .Y( \ld_in_ah[0] ), .PADPIN(LD[0]) ); bscan_cell pad139_jtag ( .PAD_OUT(\ld_out_jtag[3] ), .PAD_ENB(pad139_en), .PAD_IN(\ld_in_ah[3] ), .CORE_ENBZ(ld_enlo_az), .CORE_IN( \ld_out_ah[3] ), .SCAN_OUT(pad139_sout), .SCAN_IN(pad138_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(ld_enlo_jtag), .HI_Z(hiz_jtag_east) ); ipb_ph_in_5t_s pad206 ( .PADPIN(TC[9]), .Y(\tc_ah[9] ) ); bscan_cell pad126_jtag ( .PAD_OUT(pcix_ads_jtag), .PAD_ENB(pad126_en), .PAD_IN(pcix_ads_jtag), .CORE_ENBZ(1'b0), .CORE_IN(pcix_ads_l), .SCAN_OUT(pad126_sout), .SCAN_IN(pad124_sout), .SHIFTDR(shift_dr_south ), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE( mode_jtag_south), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_south) ); ipb_ph_in_5t_s pad221 ( .PADPIN(TS[11]), .Y(\ts_ah[11] ) ); ipb_ph_in_5t_s pad52 ( .PADPIN(RS[6]), .Y(\rs_ah[6] ) ); bscan_cntl_cell pcbe2_cntl ( .SCAN_IN(pad88_sout), .SYS_LOGIC_CNTL( pci_cbe_en_l), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .SHIFTDR(shift_dr_south), .RESET(rst_jtag_south), .SCAN_OUT( pcbe2_cntl_sout), .DIR_CNTL(pcbe2_en_jtag) ); bscan_cell pad26_jtag ( .PAD_IN(\tc_ah[3] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad26_sout), .SCAN_IN(pad25_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_vd_all pad181 ( .VDDCORE(VDD) ); core core ( .LD_OUT_AH({\ld_out_ah[15] , \ld_out_ah[14] , \ld_out_ah[13] , \ld_out_ah[12] , \ld_out_ah[11] , \ld_out_ah[10] , \ld_out_ah[9] , \ld_out_ah[8] , \ld_out_ah[7] , \ld_out_ah[6] , \ld_out_ah[5] , \ld_out_ah[4] , \ld_out_ah[3] , \ld_out_ah[2] , \ld_out_ah[1] , \ld_out_ah[0] }), .LD_ENHI_AZ(ld_enhi_az), .LD_ENLO_AZ(ld_enlo_az), .LA_OUT_RH({\la_out_rh[19] , \la_out_rh[18] , \la_out_rh[17] , \la_out_rh[16] , \la_out_rh[15] , \la_out_rh[14] , \la_out_rh[13] , \la_out_rh[12] , \la_out_rh[11] , \la_out_rh[10] , \la_out_rh[9] , \la_out_rh[8] , \la_out_rh[7] , \la_out_rh[6] , \la_out_rh[5] , \la_out_rh[4] , \la_out_rh[3] , \la_out_rh[2] , \la_out_rh[1] , \la_out_rh[0] }), .LA_EN_RZ(la_en_rz), .LWR_OUT_RZ(lwr_out_rz), .LWR_EN_RZ(lwr_en_rz), .LRD_OUT_RZ(lrd_out_rz), .LRD_EN_RZ(lrd_en_rz), .LBHE_RZ(lbhe_rz), .LBHE_EN_RZ(lbhe_en_rz), .LHOLD_RH(lhold_rh), .LBGACK_RZ(lbgack_rz), .LMS_AZ(lms_az), .LCLKE_RZ(lclke_rz), .LINT_OUT_RZ(lint_out_rz), .LD_IN_AH({\ld_in_ah[15] , \ld_in_ah[14] , \ld_in_ah[13] , \ld_in_ah[12] , \ld_in_ah[11] , \ld_in_ah[10] , \ld_in_ah[9] , \ld_in_ah[8] , \ld_in_ah[7] , \ld_in_ah[6] , \ld_in_ah[5] , \ld_in_ah[4] , \ld_in_ah[3] , \ld_in_ah[2] , \ld_in_ah[1] , \ld_in_ah[0] }), .LA_IN_AH({\la_in_ah[19] , \la_in_ah[18] , \la_in_ah[17] , \la_in_ah[16] , \la_in_ah[15] , \la_in_ah[14] , \la_in_ah[13] , \la_in_ah[12] , \la_in_ah[11] , \la_in_ah[10] , \la_in_ah[9] , \la_in_ah[8] , \la_in_ah[7] , \la_in_ah[6] , \la_in_ah[5] , \la_in_ah[4] , \la_in_ah[3] , \la_in_ah[2] , \la_in_ah[1] , \la_in_ah[0] }), .LWR_IN_AZ(lwr_in_az), .LRD_IN_AZ(lrd_in_az), .LIM_AH(lim_ah), .LMS_AH(lms_ah), .LRDY_AZ( lrdy_az), .LCS_AZ(lcs_az), .LHLDA_AH(lhlda_ah), .LINT_IN_AZ(lint_in_az ), .PCI_AD_OUT({\pci_ad_out[31] , \pci_ad_out[30] , \pci_ad_out[29] , \pci_ad_out[28] , \pci_ad_out[27] , \pci_ad_out[26] , \pci_ad_out[25] , \pci_ad_out[24] , \pci_ad_out[23] , \pci_ad_out[22] , \pci_ad_out[21] , \pci_ad_out[20] , \pci_ad_out[19] , \pci_ad_out[18] , \pci_ad_out[17] , \pci_ad_out[16] , \pci_ad_out[15] , \pci_ad_out[14] , \pci_ad_out[13] , \pci_ad_out[12] , \pci_ad_out[11] , \pci_ad_out[10] , \pci_ad_out[9] , \pci_ad_out[8] , \pci_ad_out[7] , \pci_ad_out[6] , \pci_ad_out[5] , \pci_ad_out[4] , \pci_ad_out[3] , \pci_ad_out[2] , \pci_ad_out[1] , \pci_ad_out[0] }), .PCI_CBE_OUT_L({\pci_cbe_out_l[3] , \pci_cbe_out_l[2] , \pci_cbe_out_l[1] , \pci_cbe_out_l[0] }), .PCI_FRAME_OUT_L(pci_frame_out_l), .PCI_IRDY_OUT_L(pci_irdy_out_l), .PCI_TRDY_OUT_L(pci_trdy_out_l), .PCI_STOP_OUT_L(pci_stop_out_l), .PCI_DEVSEL_OUT_L(pci_devsel_out_l), .PCI_PAR_OUT(pci_par_out), .PCI_PERR_OUT_L(pci_perr_out_l), .PCIX_ADS_L(pcix_ads_l), .PCIX_DS_L( pcix_ds_l), .PCIX_BLAST_L(pcix_blast_l), .PCI_SERR_L(pci_serr_l), .PCI_REQ_L(pci_req_l), .PCI_FRAME_EN_L(pci_frame_en_l), .PCI_IRDY_EN_L(pci_irdy_en_l), .PCI_CBE_EN_L(pci_cbe_en_l), .PCI_AD_EN_L(pci_ad_en_l), .PCI_PAR_EN_L(pci_par_en_l), .PCI_TRGT_EN_L(pci_trgt_en_l), .PCI_PERR_EN_L(pci_perr_en_l), .PCI_AD_IN({\pci_ad_in[31] , \pci_ad_in[30] , \pci_ad_in[29] , \pci_ad_in[28] , \pci_ad_in[27] , \pci_ad_in[26] , \pci_ad_in[25] , \pci_ad_in[24] , \pci_ad_in[23] , \pci_ad_in[22] , \pci_ad_in[21] , \pci_ad_in[20] , \pci_ad_in[19] , \pci_ad_in[18] , \pci_ad_in[17] , \pci_ad_in[16] , \pci_ad_in[15] , \pci_ad_in[14] , \pci_ad_in[13] , \pci_ad_in[12] , \pci_ad_in[11] , \pci_ad_in[10] , \pci_ad_in[9] , \pci_ad_in[8] , \pci_ad_in[7] , \pci_ad_in[6] , \pci_ad_in[5] , \pci_ad_in[4] , \pci_ad_in[3] , \pci_ad_in[2] , \pci_ad_in[1] , \pci_ad_in[0] }), .PCI_CBE_IN_L({\pci_cbe_in_l[3] , \pci_cbe_in_l[2] , \pci_cbe_in_l[1] , \pci_cbe_in_l[0] }), .PCI_FRAME_IN_L(pci_frame_in_l ), .PCI_IRDY_IN_L(pci_irdy_in_l), .PCI_TRDY_IN_L(pci_trdy_in_l), .PCI_STOP_IN_L(pci_stop_in_l), .PCI_DEVSEL_IN_L(pci_devsel_in_l), .PCI_PAR_IN(pci_par_in), .PCI_PERR_IN_L(pci_perr_in_l), .PCI_GNT_L( pci_gnt_l), .PCI_IDSEL(pci_idsel), .PCI_CLK(pci_clk), .PCI_RST(pci_rst ), .PCI_RSTZ(pci_rstz), .PCI_66MHZ_CAPABLE_AH(pci_66mhz_capable_ah), .SYSCLK_C(sysclk_c), .TD_AH({\td_ah[15] , \td_ah[14] , \td_ah[13] , \td_ah[12] , \td_ah[11] , \td_ah[10] , \td_ah[9] , \td_ah[8] , \td_ah[7] , \td_ah[6] , \td_ah[5] , \td_ah[4] , \td_ah[3] , \td_ah[2] , \td_ah[1] , \td_ah[0] }), .RC_AH({\rc_ah[15] , \rc_ah[14] , \rc_ah[13] , \rc_ah[12] , \rc_ah[11] , \rc_ah[10] , \rc_ah[9] , \rc_ah[8] , \rc_ah[7] , \rc_ah[6] , \rc_ah[5] , \rc_ah[4] , \rc_ah[3] , \rc_ah[2] , \rc_ah[1] , \rc_ah[0] }), .RD_AH({\rd_ah[15] , \rd_ah[14] , \rd_ah[13] , \rd_ah[12] , \rd_ah[11] , \rd_ah[10] , \rd_ah[9] , \rd_ah[8] , \rd_ah[7] , \rd_ah[6] , \rd_ah[5] , \rd_ah[4] , \rd_ah[3] , \rd_ah[2] , \rd_ah[1] , \rd_ah[0] }), .RS_AH({\rs_ah[15] , \rs_ah[14] , \rs_ah[13] , \rs_ah[12] , \rs_ah[11] , \rs_ah[10] , \rs_ah[9] , \rs_ah[8] , \rs_ah[7] , \rs_ah[6] , \rs_ah[5] , \rs_ah[4] , \rs_ah[3] , \rs_ah[2] , \rs_ah[1] , \rs_ah[0] }), .TC_AH({\tc_ah[15] , \tc_ah[14] , \tc_ah[13] , \tc_ah[12] , \tc_ah[11] , \tc_ah[10] , \tc_ah[9] , \tc_ah[8] , \tc_ah[7] , \tc_ah[6] , \tc_ah[5] , \tc_ah[4] , \tc_ah[3] , \tc_ah[2] , \tc_ah[1] , \tc_ah[0] }), .TS_AH({\ts_ah[15] , \ts_ah[14] , \ts_ah[13] , \ts_ah[12] , \ts_ah[11] , \ts_ah[10] , \ts_ah[9] , \ts_ah[8] , \ts_ah[7] , \ts_ah[6] , \ts_ah[5] , \ts_ah[4] , \ts_ah[3] , \ts_ah[2] , \ts_ah[1] , \ts_ah[0] }) ); ipb_ph_vs_all pad70_extra ( .GNDCORE(VSS) ); ipb_ph_bi_08_5t_s pad75 ( .ENB(pad75_en), .IN0(\pci_ad_out_jtag[27] ), .Y( \pci_ad_in[27] ), .PADPIN(PAD[27]) ); ipb_ph_bi_04_5t_s pad143 ( .ENB(pad143_en), .IN0(\ld_out_jtag[7] ), .Y( \ld_in_ah[7] ), .PADPIN(LD[7]) ); bscan_cell pad234_jtag ( .PAD_IN(\rs_ah[13] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad234_sout), .SCAN_IN(pad233_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_bi_04_5t_s pad151 ( .ENB(pad151_en), .IN0(\ld_out_jtag[13] ), .Y( \ld_in_ah[13] ), .PADPIN(LD[13]) ); ipb_ph_ou_04_5t pad164 ( .ENB(pad164_en), .IN0(pci_clk_jtag), .PADPIN(LCLK ) ); ipb_ph_ou_04_5t pad254 ( .ENB(1'b1), .IN0(1'b0) ); ipb_ph_in_5t_s pad40 ( .PADPIN(TC[4]), .Y(\tc_ah[4] ) ); ipb_ph_bi_04_5t_s pad176 ( .ENB(pad176_en), .IN0(\la_out_jtag[5] ), .Y( \la_in_ah[5] ), .PADPIN(LA[5]) ); bscan_cell pad36_jtag ( .PAD_IN(\rc_ah[4] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad36_sout), .SCAN_IN(pad28_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_vs_all pad246 ( .GNDCORE(VSS) ); bscan_cell pad120_jtag ( .PAD_OUT(\pci_ad_out_jtag[3] ), .PAD_ENB( pad120_en), .PAD_IN(\pci_ad_in[3] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN(\pci_ad_out[3] ), .SCAN_OUT(pad120_sout), .SCAN_IN( pad119_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL( pad_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad104_jtag ( .PAD_OUT(\pci_ad_out_jtag[15] ), .PAD_ENB( pad104_en), .PAD_IN(\pci_ad_in[15] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN(\pci_ad_out[15] ), .SCAN_OUT(pad104_sout), .SCAN_IN( pad102_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL( pad_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_in_5t_s pad67 ( .PADPIN(PGNT), .Y(pci_gnt_l) ); bscan_cell pad12_jtag ( .PAD_IN(\tc_ah[1] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad12_sout), .SCAN_IN(pad11_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_ou_04_5t pad193 ( .ENB(1'b1), .IN0(1'b0) ); ipb_ph_ou_04_5t pad6 ( .ENB(pad6_en), .IN0(\td_jtag_ah[0] ), .PADPIN(TD[0] ) ); ipb_ph_vd_all pad7_extra ( .VDDCORE(VDD) ); ipb_ph_in_5t_s pad12 ( .PADPIN(TC[1]), .Y(\tc_ah[1] ) ); ipb_ph_vd_all pad35 ( .VDDCORE(VDD) ); ipb_ph_bi_08_5t_s pad82 ( .ENB(pad82_en), .IN0(\pci_ad_out_jtag[22] ), .Y( \pci_ad_in[22] ), .PADPIN(PAD[22]) ); bscan_cell pad224_jtag ( .PAD_IN(\rc_ah[12] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad224_sout), .SCAN_IN(pad222_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_vd_all pad99 ( .VDDCORE(VDD) ); ipb_ph_vs_all pad103 ( .GNDCORE(VSS) ); ipb_ph_bi_08_5t_s pad118 ( .ENB(pad118_en), .IN0(\pci_ad_out_jtag[5] ), .Y(\pci_ad_in[5] ), .PADPIN(PAD[5]) ); bscan_cell pad200_jtag ( .PAD_OUT(\td_jtag_ah[8] ), .PAD_ENB(pad200_en), .PAD_IN(\td_jtag_ah[8] ), .CORE_ENBZ(1'b0), .CORE_IN(\td_ah[8] ), .SCAN_OUT(pad200_sout), .SCAN_IN(pad199_sout), .SHIFTDR(shift_dr_north ), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE( mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_in_5t_s pad228 ( .PADPIN(TC[12]), .Y(\tc_ah[12] ) ); ipb_ph_in_5t_s pad214 ( .PADPIN(TC[10]), .Y(\tc_ah[10] ) ); ipb_ph_bi_04_5t_s_od pad124 ( .ENB(pad124_en), .IN0(pinta_out_jtag), .PADPIN(PINTA) ); ipb_ph_in_5t_s pad233 ( .PADPIN(RC[13]), .Y(\rc_ah[13] ) ); bscan_cell pad216_jtag ( .PAD_OUT(\td_jtag_ah[10] ), .PAD_ENB(pad216_en), .PAD_IN(\td_jtag_ah[10] ), .CORE_ENBZ(1'b0), .CORE_IN(\td_ah[10] ), .SCAN_OUT(pad216_sout), .SCAN_IN(pad215_sout), .SHIFTDR(shift_dr_north ), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE( mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cntl_cell pstop_cntl ( .SCAN_IN(pad96_sout), .SYS_LOGIC_CNTL( pci_trgt_en_l), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .SHIFTDR(shift_dr_south), .RESET(rst_jtag_south), .SCAN_OUT( pstop_cntl_sout), .DIR_CNTL(pstop_en_jtag) ); ipb_ph_bi_04_5t_s pad188 ( .ENB(pad188_en), .IN0(\la_out_jtag[15] ), .Y( \la_in_ah[15] ), .PADPIN(LA[15]) ); ipb_ph_vd_all pad201_extra ( .VDDCORE(VDD) ); bscan_cell pad20_jtag ( .PAD_IN(\tc_ah[2] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad20_sout), .SCAN_IN(pad19_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad112_jtag ( .PAD_OUT(\pci_cbe_out_jtag[0] ), .PAD_ENB( pad112_en), .PAD_IN(\pci_cbe_in_l[0] ), .CORE_ENBZ(pci_cbe_en_l), .CORE_IN(\pci_cbe_out_l[0] ), .SCAN_OUT(pad112_sout), .SCAN_IN( pcbe0_cntl_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL( pcbe0_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad136_jtag ( .PAD_OUT(\ld_out_jtag[0] ), .PAD_ENB(pad136_en), .PAD_IN(\ld_in_ah[0] ), .CORE_ENBZ(ld_enlo_az), .CORE_IN( \ld_out_ah[0] ), .SCAN_OUT(pad136_sout), .SCAN_IN(ld_cntl_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(ld_enlo_jtag), .HI_Z(hiz_jtag_east) ); ipb_ph_vd_all pad15 ( .VDDCORE(VDD) ); bscan_cntl_cell ppar_cntl ( .SCAN_IN(pad100_sout), .SYS_LOGIC_CNTL( pci_par_en_l), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .SHIFTDR(shift_dr_south), .RESET(rst_jtag_south), .SCAN_OUT( ppar_cntl_sout), .DIR_CNTL(ppar_en_jtag) ); bscan_cell pad218_jtag ( .PAD_IN(\rs_ah[11] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad218_sout), .SCAN_IN(pad217_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_bi_08_5t_s pad104 ( .ENB(pad104_en), .IN0(\pci_ad_out_jtag[15] ), .Y(\pci_ad_in[15] ), .PADPIN(PAD[15]) ); bscan_cell pad207_jtag ( .PAD_IN(\ts_ah[9] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad207_sout), .SCAN_IN(pad206_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_bi_08_5t_s pad123 ( .ENB(pad123_en), .IN0(\pci_ad_out_jtag[0] ), .Y(\pci_ad_in[0] ), .PADPIN(PAD[0]) ); ipb_ph_in_5t_s pad213 ( .PADPIN(RD[10]), .Y(\rd_ah[10] ) ); ipb_ph_in_5t_s pad234 ( .PADPIN(RS[13]), .Y(\rs_ah[13] ) ); bscan_cell pad127_jtag ( .PAD_OUT(pcix_ds_jtag), .PAD_ENB(pad127_en), .PAD_IN(pcix_ds_jtag), .CORE_ENBZ(1'b0), .CORE_IN(pcix_ds_l), .SCAN_OUT(pad127_sout), .SCAN_IN(pad126_sout), .SHIFTDR(shift_dr_south ), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE( mode_jtag_south), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_south) ); bscan_cell pad138_jtag ( .PAD_OUT(\ld_out_jtag[2] ), .PAD_ENB(pad138_en), .PAD_IN(\ld_in_ah[2] ), .CORE_ENBZ(ld_enlo_az), .CORE_IN( \ld_out_ah[2] ), .SCAN_OUT(pad138_sout), .SCAN_IN(pad137_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(ld_enlo_jtag), .HI_Z(hiz_jtag_east) ); bscan_cell pad38_jtag ( .PAD_IN(\rd_ah[4] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad38_sout), .SCAN_IN(pad37_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_ou_04_5t pad32 ( .ENB(1'b1), .IN0(1'b0) ); ipb_ph_ou_04_5t pad29 ( .ENB(1'b1), .IN0(1'b0) ); ipb_ph_vd_all pad7 ( .VDDCORE(VDD) ); ipb_ph_vs_all pad8_extra ( .GNDCORE(VSS) ); bscan_cntl_cell pcbe3_cntl ( .SCAN_IN(pad78_sout), .SYS_LOGIC_CNTL( pci_cbe_en_l), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .SHIFTDR(shift_dr_south), .RESET(rst_jtag_south), .SCAN_OUT( pcbe3_cntl_sout), .DIR_CNTL(pcbe3_en_jtag) ); ipb_ph_bi_04_5t_s pad138 ( .ENB(pad138_en), .IN0(\ld_out_jtag[2] ), .Y( \ld_in_ah[2] ), .PADPIN(LD[2]) ); ipb_ph_ou_04_5t pad194 ( .ENB(1'b1), .IN0(1'b0) ); ipb_ph_ou_04_5t pad208 ( .ENB(pad208_en), .IN0(\td_jtag_ah[9] ), .PADPIN( TD[9]) ); ipb_ph_in_5t_s pad60 ( .PADPIN(TC[7]), .Y(\tc_ah[7] ) ); bscan_cntl_cell pad_cntl ( .SCAN_IN(pad68_sout), .SYS_LOGIC_CNTL( pci_ad_en_l), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .SHIFTDR(shift_dr_south), .RESET(rst_jtag_south), .SCAN_OUT( pad_cntl_sout), .DIR_CNTL(pad_en_jtag) ); ipb_ph_bi_08_5t_s pad85 ( .ENB(pad85_en), .IN0(\pci_ad_out_jtag[19] ), .Y( \pci_ad_in[19] ), .PADPIN(PAD[19]) ); bscan_cell pad27_jtag ( .PAD_IN(\ts_ah[3] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad27_sout), .SCAN_IN(pad26_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_vd_all pad144_extra ( .VDDCORE(VDD) ); ipb_ph_bi_04_5t_s pad171 ( .ENB(pad171_en), .IN0(\la_out_jtag[0] ), .Y( \la_in_ah[0] ), .PADPIN(LA[0]) ); ipb_ph_in_5t_s pad241 ( .PADPIN(RD[14]), .Y(\rd_ah[14] ) ); bscan_cell pad211_jtag ( .PAD_IN(\rc_ah[10] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad211_sout), .SCAN_IN(pad208_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_ou_04_5t pad156 ( .ENB(1'b1), .IN0(1'b0) ); bscan_cell pad235_jtag ( .PAD_IN(\rd_ah[13] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad235_sout), .SCAN_IN(pad234_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_vd_all pad227_extra ( .VDDCORE(VDD) ); ipb_ph_in_5t_s pad47 ( .PADPIN(TS[5]), .Y(\ts_ah[5] ) ); ipb_ph_bi_08_5t_s pad72 ( .ENB(pad72_en), .IN0(\pci_ad_out_jtag[30] ), .Y( \pci_ad_in[30] ), .PADPIN(PAD[30]) ); bscan_cell pad28_jtag ( .PAD_OUT(\td_jtag_ah[3] ), .PAD_ENB(pad28_en), .PAD_IN(\td_jtag_ah[3] ), .CORE_ENBZ(1'b0), .CORE_IN(\td_ah[3] ), .SCAN_OUT(pad28_sout), .SCAN_IN(pad27_sout), .SHIFTDR(shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west ), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_vs_all pad16_extra ( .GNDCORE(VSS) ); ipb_ph_in_5t_s pad55 ( .PADPIN(TS[6]), .Y(\ts_ah[6] ) ); bscan_cell pad13_jtag ( .PAD_IN(\ts_ah[1] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad13_sout), .SCAN_IN(pad12_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_vd_all pad163 ( .VDDCORE(VDD) ); bscan_cell pad105_jtag ( .PAD_OUT(\pci_ad_out_jtag[14] ), .PAD_ENB( pad105_en), .PAD_IN(\pci_ad_in[14] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN(\pci_ad_out[14] ), .SCAN_OUT(pad105_sout), .SCAN_IN( pad104_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL( pad_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad121_jtag ( .PAD_OUT(\pci_ad_out_jtag[2] ), .PAD_ENB( pad121_en), .PAD_IN(\pci_ad_in[2] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN(\pci_ad_out[2] ), .SCAN_OUT(pad121_sout), .SCAN_IN( pad120_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL( pad_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_ou_04_5t pad253 ( .ENB(1'b1), .IN0(1'b0) ); ipb_ph_bi_08_5t_s pad97 ( .ENB(pad97_en), .IN0(pci_stop_out_jtag), .Y( pci_stop_in_l), .PADPIN(PSTOP) ); ipb_ph_vd_all pad144 ( .VDDCORE(VDD) ); bscan_cell pad37_jtag ( .PAD_IN(\rs_ah[4] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad37_sout), .SCAN_IN(pad36_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_vs_all pad145_extra ( .GNDCORE(VSS) ); ipb_ph_bi_04_5t_s pad186 ( .ENB(pad186_en), .IN0(\la_out_jtag[13] ), .Y( \la_in_ah[13] ), .PADPIN(LA[13]) ); bscan_cell pad225_jtag ( .PAD_IN(\rs_ah[12] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad225_sout), .SCAN_IN(pad224_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_in_5t_s pad20 ( .PADPIN(TC[2]), .Y(\tc_ah[2] ) ); bscan_cell pad233_jtag ( .PAD_IN(\rc_ah[13] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad233_sout), .SCAN_IN(pad230_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_bi_08_5t_s pad116 ( .ENB(pad116_en), .IN0(\pci_ad_out_jtag[7] ), .Y(\pci_ad_in[7] ), .PADPIN(PAD[7]) ); bscan_cell pad208_jtag ( .PAD_OUT(\td_jtag_ah[9] ), .PAD_ENB(pad208_en), .PAD_IN(\td_jtag_ah[9] ), .CORE_ENBZ(1'b0), .CORE_IN(\td_ah[9] ), .SCAN_OUT(pad208_sout), .SCAN_IN(pad207_sout), .SHIFTDR(shift_dr_north ), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE( mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_bi_04_5t_s_up pad131 ( .ENB(1'b1), .IN0(1'b0), .Y(jtrst_ah), .PADPIN(JTRST) ); ipb_ph_vd_all pad201 ( .VDDCORE(VDD) ); ipb_ph_in_5t_s pad226 ( .PADPIN(RD[12]), .Y(\rd_ah[12] ) ); bscan_cell pad217_jtag ( .PAD_IN(\rc_ah[11] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad217_sout), .SCAN_IN(pad216_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_vd_all pad163_extra ( .VDDCORE(VDD) ); ipb_ph_ou_04_5t pad28 ( .ENB(pad28_en), .IN0(\td_jtag_ah[3] ), .PADPIN(TD [3]) ); ipb_ph_in_5t_s pad46 ( .PADPIN(TC[5]), .Y(\tc_ah[5] ) ); ipb_ph_in_5t_s pad61 ( .PADPIN(TS[7]), .Y(\ts_ah[7] ) ); ipb_ph_vd_all pad69 ( .VDDCORE(VDD) ); ipb_ph_bi_04_5t_s pad178 ( .ENB(pad178_en), .IN0(\la_out_jtag[7] ), .Y( \la_in_ah[7] ), .PADPIN(LA[7]) ); bscan_cell pad21_jtag ( .PAD_IN(\ts_ah[2] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad21_sout), .SCAN_IN(pad20_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_in_5t_s pad248 ( .PADPIN(RS[15]), .Y(\rs_ah[15] ) ); bscan_cell pad137_jtag ( .PAD_OUT(\ld_out_jtag[1] ), .PAD_ENB(pad137_en), .PAD_IN(\ld_in_ah[1] ), .CORE_ENBZ(ld_enlo_az), .CORE_IN( \ld_out_ah[1] ), .SCAN_OUT(pad137_sout), .SCAN_IN(pad136_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(ld_enlo_jtag), .HI_Z(hiz_jtag_east) ); bscan_cell pad128_jtag ( .PAD_OUT(pcix_blast_jtag), .PAD_ENB(pad128_en), .PAD_IN(pcix_blast_jtag), .CORE_ENBZ(1'b0), .CORE_IN(pcix_blast_l), .SCAN_OUT(so_bs), .SCAN_IN(pad127_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE( mode_jtag_south), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_south) ); ipb_ph_ou_04_5t pad157 ( .ENB(pad157_en), .IN0(lhold_jtag), .PADPIN(LHOLD) ); ipb_ph_bi_04_5t_s pad170 ( .ENB(pad170_en), .IN0(lrd_out_jtag), .Y( lrd_in_az), .PADPIN(LRD) ); ipb_ph_in_5t_s pad240 ( .PADPIN(RS[14]), .Y(\rs_ah[14] ) ); bscan_cell pad151_jtag ( .PAD_OUT(\ld_out_jtag[13] ), .PAD_ENB(pad151_en), .PAD_IN(\ld_in_ah[13] ), .CORE_ENBZ(ld_enhi_az), .CORE_IN( \ld_out_ah[13] ), .SCAN_OUT(pad151_sout), .SCAN_IN(pad150_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(ld_enlo_jtag), .HI_Z(hiz_jtag_east) ); ipb_ph_ou_04_5t pad14 ( .ENB(pad14_en), .IN0(\td_jtag_ah[1] ), .PADPIN(TD [1]) ); ipb_ph_bi_04_5t_s pad139 ( .ENB(pad139_en), .IN0(\ld_out_jtag[3] ), .Y( \ld_in_ah[3] ), .PADPIN(LD[3]) ); ipb_ph_in_5t_s pad195 ( .PADPIN(RC[8]), .Y(\rc_ah[8] ) ); bscan_cell pad47_jtag ( .PAD_IN(\ts_ah[5] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad47_sout), .SCAN_IN(pad46_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_bi_08_5t_s pad84 ( .ENB(pad84_en), .IN0(\pci_ad_out_jtag[20] ), .Y( \pci_ad_in[20] ), .PADPIN(PAD[20]) ); ipb_ph_vd_all pad209 ( .VDDCORE(VDD) ); bscan_cell pad58_jtag ( .PAD_IN(\rs_ah[7] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad58_sout), .SCAN_IN(pad57_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad85_jtag ( .PAD_OUT(\pci_ad_out_jtag[19] ), .PAD_ENB(pad85_en ), .PAD_IN(\pci_ad_in[19] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN( \pci_ad_out[19] ), .SCAN_OUT(pad85_sout), .SCAN_IN(pad84_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pad_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_bi_08_5t_s pad105 ( .ENB(pad105_en), .IN0(\pci_ad_out_jtag[14] ), .Y(\pci_ad_in[14] ), .PADPIN(PAD[14]) ); bscan_cell pad93_jtag ( .PAD_OUT(pci_frame_out_jtag), .PAD_ENB(pad93_en), .PAD_IN(pci_frame_in_l), .CORE_ENBZ(pci_frame_en_l), .CORE_IN( pci_frame_out_l), .SCAN_OUT(pad93_sout), .SCAN_IN(pframe_cntl_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pframe_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad158_jtag ( .PAD_IN(lhlda_ah), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad158_sout), .SCAN_IN(pad157_sout), .SHIFTDR( shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_east) ); bscan_cell pad175_jtag ( .PAD_OUT(\la_out_jtag[4] ), .PAD_ENB(pad175_en), .PAD_IN(\la_in_ah[4] ), .CORE_ENBZ(la_en_rz), .CORE_IN(\la_out_rh[4] ), .SCAN_OUT(pad175_sout), .SCAN_IN(pad174_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east ), .DIR_CNTL(la_en_jtag), .HI_Z(hiz_jtag_east) ); ipb_ph_in_5t_s pad235 ( .PADPIN(RD[13]), .Y(\rd_ah[13] ) ); ipb_ph_in_5t_s pad212 ( .PADPIN(RS[10]), .Y(\rs_ah[10] ) ); bscan_cell pad185_jtag ( .PAD_OUT(\la_out_jtag[12] ), .PAD_ENB(pad185_en), .PAD_IN(\la_in_ah[12] ), .CORE_ENBZ(la_en_rz), .CORE_IN( \la_out_rh[12] ), .SCAN_OUT(pad185_sout), .SCAN_IN(pad184_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(la_en_jtag), .HI_Z( hiz_jtag_east) ); ipb_ph_bi_08_5t_s pad122 ( .ENB(pad122_en), .IN0(\pci_ad_out_jtag[1] ), .Y(\pci_ad_in[1] ), .PADPIN(PAD[1]) ); bscan_cell pad75_jtag ( .PAD_OUT(\pci_ad_out_jtag[27] ), .PAD_ENB(pad75_en ), .PAD_IN(\pci_ad_in[27] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN( \pci_ad_out[27] ), .SCAN_OUT(pad75_sout), .SCAN_IN(pad74_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pad_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cntl_cell lint_cntl ( .SCAN_IN(pad159_sout), .SYS_LOGIC_CNTL(lms_az), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .SHIFTDR( shift_dr_east), .RESET(rst_jtag_east), .SCAN_OUT(lint_cntl_sout), .DIR_CNTL(lint_en_jtag) ); bscan_cell pad51_jtag ( .PAD_IN(\rc_ah[6] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad51_sout), .SCAN_IN(pad48_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_in_5t_s pad21 ( .PADPIN(TS[2]), .Y(\ts_ah[2] ) ); ipb_ph_bi_04_5t_s pad179 ( .ENB(pad179_en), .IN0(\la_out_jtag[8] ), .Y( \la_in_ah[8] ), .PADPIN(LA[8]) ); bscan_cell pad2_jtag ( .PAD_IN(\rs_ah[0] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad2_sout), .SCAN_IN(pad1_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad147_jtag ( .PAD_OUT(\ld_out_jtag[9] ), .PAD_ENB(pad147_en), .PAD_IN(\ld_in_ah[9] ), .CORE_ENBZ(ld_enhi_az), .CORE_IN( \ld_out_ah[9] ), .SCAN_OUT(pad147_sout), .SCAN_IN(pad146_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(ld_enlo_jtag), .HI_Z(hiz_jtag_east) ); ipb_ph_ou_04_5t pad33 ( .ENB(1'b1), .IN0(1'b0) ); bscan_cell pad83_jtag ( .PAD_OUT(\pci_ad_out_jtag[21] ), .PAD_ENB(pad83_en ), .PAD_IN(\pci_ad_in[21] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN( \pci_ad_out[21] ), .SCAN_OUT(pad83_sout), .SCAN_IN(pad82_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pad_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad243_jtag ( .PAD_IN(\ts_ah[14] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad243_sout), .SCAN_IN(pad242_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cell pad148_jtag ( .PAD_OUT(\ld_out_jtag[10] ), .PAD_ENB(pad148_en), .PAD_IN(\ld_in_ah[10] ), .CORE_ENBZ(ld_enhi_az), .CORE_IN( \ld_out_ah[10] ), .SCAN_OUT(pad148_sout), .SCAN_IN(pad147_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(ld_enlo_jtag), .HI_Z(hiz_jtag_east) ); bscan_cell pad173_jtag ( .PAD_OUT(\la_out_jtag[2] ), .PAD_ENB(pad173_en), .PAD_IN(\la_in_ah[2] ), .CORE_ENBZ(la_en_rz), .CORE_IN(\la_out_rh[2] ), .SCAN_OUT(pad173_sout), .SCAN_IN(pad172_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east ), .DIR_CNTL(la_en_jtag), .HI_Z(hiz_jtag_east) ); bscan_cell pad195_jtag ( .PAD_IN(\rc_ah[8] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad195_sout), .SCAN_IN(scan_in_north), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_in_5t_s pad249 ( .PADPIN(RD[15]), .Y(\rd_ah[15] ) ); ipb_ph_ou_04_5t pad68 ( .ENB(preq_en), .IN0(pci_req_jtag), .PADPIN(PREQ) ); bscan_cell pad41_jtag ( .PAD_IN(\ts_ah[4] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad41_sout), .SCAN_IN(pad40_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad65_jtag ( .PAD_IN(pci_rst), .CORE_ENBZ(1'b0), .CORE_IN(1'b0), .SCAN_OUT(pad65_sout), .SCAN_IN(scan_in_south), .SHIFTDR( shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_south) ); bscan_cell pad157_jtag ( .PAD_OUT(lhold_jtag), .PAD_ENB(pad157_en), .PAD_IN(lhold_jtag), .CORE_ENBZ(lms_ah), .CORE_IN(lhold_rh), .SCAN_OUT(pad157_sout), .SCAN_IN(pad155_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east ), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_east) ); ipb_ph_vd_all pad89_extra ( .VDDCORE(VDD) ); ipb_ph_bi_08_5t_s pad117 ( .ENB(pad117_en), .IN0(\pci_ad_out_jtag[6] ), .Y(\pci_ad_in[6] ), .PADPIN(PAD[6]) ); ipb_ph_in_5t_s pad130 ( .PADPIN(JTCLK), .Y(jtclk_c) ); ipb_ph_ou_04_5t pad200 ( .ENB(pad200_en), .IN0(\td_jtag_ah[8] ), .PADPIN( TD[8]) ); ipb_ph_vd_all pad227 ( .VDDCORE(VDD) ); ipb_ph_vd_all pad209_extra ( .VDDCORE(VDD) ); ipb_ph_in_5t_s pad9 ( .PADPIN(RC[1]), .Y(\rc_ah[1] ) ); ipb_ph_in_5t_s pad26 ( .PADPIN(TC[3]), .Y(\tc_ah[3] ) ); ipb_ph_vs_all pad39_extra ( .GNDCORE(VSS) ); bscan_cell pad4_jtag ( .PAD_IN(\tc_ah[0] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad4_sout), .SCAN_IN(pad3_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_in_5t_s pad54 ( .PADPIN(TC[6]), .Y(\tc_ah[6] ) ); ipb_ph_bi_08_5t_s pad73 ( .ENB(pad73_en), .IN0(\pci_ad_out_jtag[29] ), .Y( \pci_ad_in[29] ), .PADPIN(PAD[29]) ); ipb_ph_bi_08_5t_s pad96 ( .ENB(pad96_en), .IN0(pci_devsel_out_jtag), .Y( pci_devsel_in_l), .PADPIN(PDEVSEL) ); ipb_ph_bi_04_5t_s pad187 ( .ENB(pad187_en), .IN0(\la_out_jtag[14] ), .Y( \la_in_ah[14] ), .PADPIN(LA[14]) ); bscan_cell pad141_jtag ( .PAD_OUT(\ld_out_jtag[5] ), .PAD_ENB(pad141_en), .PAD_IN(\ld_in_ah[5] ), .CORE_ENBZ(ld_enlo_az), .CORE_IN( \ld_out_ah[5] ), .SCAN_OUT(pad141_sout), .SCAN_IN(pad140_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(ld_enlo_jtag), .HI_Z(hiz_jtag_east) ); bscan_cell pad57_jtag ( .PAD_IN(\rc_ah[7] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad57_sout), .SCAN_IN(pad56_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_ou_04_5t pad252 ( .ENB(pad252_en), .IN0(\td_jtag_ah[15] ), .PADPIN( TD[15]) ); ipb_ph_in_5t_s pad53 ( .PADPIN(RD[6]), .Y(\rd_ah[6] ) ); ipb_ph_in_5t_s pad162 ( .PADPIN(LRDY), .Y(lrdy_az) ); bscan_cell pad48_jtag ( .PAD_OUT(\td_jtag_ah[5] ), .PAD_ENB(pad48_en), .PAD_IN(\td_jtag_ah[5] ), .CORE_ENBZ(1'b0), .CORE_IN(\td_ah[5] ), .SCAN_OUT(pad48_sout), .SCAN_IN(pad47_sout), .SHIFTDR(shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west ), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad183_jtag ( .PAD_OUT(\la_out_jtag[10] ), .PAD_ENB(pad183_en), .PAD_IN(\la_in_ah[10] ), .CORE_ENBZ(la_en_rz), .CORE_IN( \la_out_rh[10] ), .SCAN_OUT(pad183_sout), .SCAN_IN(pad180_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(la_en_jtag), .HI_Z( hiz_jtag_east) ); ipb_ph_vs_all pad145 ( .GNDCORE(VSS) ); bscan_cell pad73_jtag ( .PAD_OUT(\pci_ad_out_jtag[29] ), .PAD_ENB(pad73_en ), .PAD_IN(\pci_ad_in[29] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN( \pci_ad_out[29] ), .SCAN_OUT(pad73_sout), .SCAN_IN(pad72_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pad_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad95_jtag ( .PAD_OUT(pci_trdy_out_jtag), .PAD_ENB(pad95_en), .PAD_IN(pci_trdy_in_l), .CORE_ENBZ(pci_trgt_en_l), .CORE_IN( pci_trdy_out_l), .SCAN_OUT(pad95_sout), .SCAN_IN(ptrdy_cntl_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(ptrdy_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_bi_08_5t_s pad74 ( .ENB(pad74_en), .IN0(\pci_ad_out_jtag[28] ), .Y( \pci_ad_in[28] ), .PADPIN(PAD[28]) ); ipb_ph_bi_04_5t_s pad142 ( .ENB(pad142_en), .IN0(\ld_out_jtag[6] ), .Y( \ld_in_ah[6] ), .PADPIN(LD[6]) ); ipb_ph_vs_all pad246_extra ( .GNDCORE(VSS) ); ipb_ph_ou_04_5t pad165 ( .ENB(1'b1), .IN0(1'b0) ); ipb_ph_vd_all pad181_extra ( .VDDCORE(VDD) ); bscan_cell pad62_jtag ( .PAD_OUT(\td_jtag_ah[7] ), .PAD_ENB(pad62_en), .PAD_IN(\td_jtag_ah[7] ), .CORE_ENBZ(1'b0), .CORE_IN(\td_ah[7] ), .SCAN_OUT(pad62_sout), .SCAN_IN(pad61_sout), .SHIFTDR(shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west ), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad84_jtag ( .PAD_OUT(\pci_ad_out_jtag[20] ), .PAD_ENB(pad84_en ), .PAD_IN(\pci_ad_in[20] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN( \pci_ad_out[20] ), .SCAN_OUT(pad84_sout), .SCAN_IN(pad83_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pad_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad174_jtag ( .PAD_OUT(\la_out_jtag[3] ), .PAD_ENB(pad174_en), .PAD_IN(\la_in_ah[3] ), .CORE_ENBZ(la_en_rz), .CORE_IN(\la_out_rh[3] ), .SCAN_OUT(pad174_sout), .SCAN_IN(pad173_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east ), .DIR_CNTL(la_en_jtag), .HI_Z(hiz_jtag_east) ); ipb_ph_bi_04_5t_s_up pad255 ( .ENB(1'b1), .IN0(1'b0) ); ipb_ph_ou_04_5t pad91 ( .ENB(1'b1), .IN0(1'b0) ); ipb_ph_bi_04_5t_s pad180 ( .ENB(pad180_en), .IN0(\la_out_jtag[9] ), .Y( \la_in_ah[9] ), .PADPIN(LA[9]) ); bscan_cell pad59_jtag ( .PAD_IN(\rd_ah[7] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad59_sout), .SCAN_IN(pad58_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad192_jtag ( .PAD_OUT(\la_out_jtag[19] ), .PAD_ENB(pad192_en), .PAD_IN(\la_in_ah[19] ), .CORE_ENBZ(la_en_rz), .CORE_IN( \la_out_rh[19] ), .SCAN_OUT(pad192_sout), .SCAN_IN(pad191_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(la_en_jtag), .HI_Z( hiz_jtag_east) ); bscan_cell pad46_jtag ( .PAD_IN(\tc_ah[5] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad46_sout), .SCAN_IN(pad45_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad150_jtag ( .PAD_OUT(\ld_out_jtag[12] ), .PAD_ENB(pad150_en), .PAD_IN(\ld_in_ah[12] ), .CORE_ENBZ(ld_enhi_az), .CORE_IN( \ld_out_ah[12] ), .SCAN_OUT(pad150_sout), .SCAN_IN(pad149_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(ld_enlo_jtag), .HI_Z(hiz_jtag_east) ); bscan_cell pad146_jtag ( .PAD_OUT(\ld_out_jtag[8] ), .PAD_ENB(pad146_en), .PAD_IN(\ld_in_ah[8] ), .CORE_ENBZ(ld_enhi_az), .CORE_IN( \ld_out_ah[8] ), .SCAN_OUT(pad146_sout), .SCAN_IN(pad143_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(ld_enlo_jtag), .HI_Z(hiz_jtag_east) ); ipb_ph_vs_all pad50_extra ( .GNDCORE(VSS) ); ipb_ph_bi_04_5t_s pad137 ( .ENB(pad137_en), .IN0(\ld_out_jtag[1] ), .Y( \ld_in_ah[1] ), .PADPIN(LD[1]) ); bscan_cell pad74_jtag ( .PAD_OUT(\pci_ad_out_jtag[28] ), .PAD_ENB(pad74_en ), .PAD_IN(\pci_ad_in[28] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN( \pci_ad_out[28] ), .SCAN_OUT(pad74_sout), .SCAN_IN(pad73_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pad_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_in_5t_s pad207 ( .PADPIN(TS[9]), .Y(\ts_ah[9] ) ); ipb_ph_in_5t_s pad220 ( .PADPIN(TC[11]), .Y(\tc_ah[11] ) ); bscan_cell pad184_jtag ( .PAD_OUT(\la_out_jtag[11] ), .PAD_ENB(pad184_en), .PAD_IN(\la_in_ah[11] ), .CORE_ENBZ(la_en_rz), .CORE_IN( \la_out_rh[11] ), .SCAN_OUT(pad184_sout), .SCAN_IN(pad183_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(la_en_jtag), .HI_Z( hiz_jtag_east) ); ipb_ph_bi_08_5t_s pad110 ( .ENB(pad110_en), .IN0(\pci_ad_out_jtag[9] ), .Y(\pci_ad_in[9] ), .PADPIN(PAD[9]) ); bscan_cell pad92_jtag ( .PAD_OUT(\pci_cbe_out_jtag[2] ), .PAD_ENB(pad92_en ), .PAD_IN(\pci_cbe_in_l[2] ), .CORE_ENBZ(pci_cbe_en_l), .CORE_IN( \pci_cbe_out_l[2] ), .SCAN_OUT(pad92_sout), .SCAN_IN(pcbe2_cntl_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pcbe2_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad159_jtag ( .PAD_OUT(lbgack_jtag), .PAD_ENB(pad159_en), .PAD_IN(lbgack_jtag), .CORE_ENBZ(lms_ah), .CORE_IN(lbgack_rz), .SCAN_OUT(pad159_sout), .SCAN_IN(pad158_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east ), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_east) ); bscan_cell pad162_jtag ( .PAD_IN(lrdy_az), .CORE_ENBZ(1'b0), .CORE_IN(1'b0 ), .SCAN_OUT(pad162_sout), .SCAN_IN(pad161_sout), .SHIFTDR( shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_east) ); ipb_ph_ou_04_5t pad159 ( .ENB(pad159_en), .IN0(lbgack_jtag), .PADPIN( LBGACK) ); bscan_cell pad242_jtag ( .PAD_IN(\tc_ah[14] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad242_sout), .SCAN_IN(pad241_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_in_5t_s pad13 ( .PADPIN(TS[1]), .Y(\ts_ah[1] ) ); ipb_ph_ou_04_5t pad48 ( .ENB(pad48_en), .IN0(\td_jtag_ah[5] ), .PADPIN(TD [5]) ); ipb_ph_vs_all pad103_extra ( .GNDCORE(VSS) ); bscan_cell pad3_jtag ( .PAD_IN(\rd_ah[0] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad3_sout), .SCAN_IN(pad2_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cntl_cell ptrdy_cntl ( .SCAN_IN(pad94_sout), .SYS_LOGIC_CNTL( pci_trgt_en_l), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .SHIFTDR(shift_dr_south), .RESET(rst_jtag_south), .SCAN_OUT( ptrdy_cntl_sout), .DIR_CNTL(ptrdy_en_jtag) ); bscan_cell pad40_jtag ( .PAD_IN(\tc_ah[4] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad40_sout), .SCAN_IN(pad38_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad82_jtag ( .PAD_OUT(\pci_ad_out_jtag[22] ), .PAD_ENB(pad82_en ), .PAD_IN(\pci_ad_in[22] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN( \pci_ad_out[22] ), .SCAN_OUT(pad82_sout), .SCAN_IN(pad81_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pad_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad172_jtag ( .PAD_OUT(\la_out_jtag[1] ), .PAD_ENB(pad172_en), .PAD_IN(\la_in_ah[1] ), .CORE_ENBZ(la_en_rz), .CORE_IN(\la_out_rh[1] ), .SCAN_OUT(pad172_sout), .SCAN_IN(pad171_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east ), .DIR_CNTL(la_en_jtag), .HI_Z(hiz_jtag_east) ); bscan_cell pad149_jtag ( .PAD_OUT(\ld_out_jtag[11] ), .PAD_ENB(pad149_en), .PAD_IN(\ld_in_ah[11] ), .CORE_ENBZ(ld_enhi_az), .CORE_IN( \ld_out_ah[11] ), .SCAN_OUT(pad149_sout), .SCAN_IN(pad148_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(ld_enlo_jtag), .HI_Z(hiz_jtag_east) ); ipb_ph_bi_08_5t_s pad98 ( .ENB(pad98_en), .IN0(pci_perr_out_jtag), .Y( pci_perr_in_l), .PADPIN(PPERR) ); ipb_ph_bi_08_5t_s pad102 ( .ENB(pad102_en), .IN0(\pci_cbe_out_jtag[1] ), .Y(\pci_cbe_in_l[1] ), .PADPIN(PCBE[1]) ); ipb_ph_in_5t_s pad125 ( .PADPIN(PCI_66MHZ_CAPABLE), .Y( pci_66mhz_capable_ah) ); ipb_ph_in_5t_s pad215 ( .PADPIN(TS[10]), .Y(\ts_ah[10] ) ); bscan_cell pad252_jtag ( .PAD_OUT(\td_jtag_ah[15] ), .PAD_ENB(pad252_en), .PAD_IN(\td_jtag_ah[15] ), .CORE_ENBZ(1'b0), .CORE_IN(\td_ah[15] ), .SCAN_OUT(pad252_sout), .SCAN_IN(pad251_sout), .SHIFTDR(shift_dr_north ), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE( mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_ou_04_5t pad232 ( .ENB(1'b1), .IN0(1'b0) ); bscan_buffer_cell bscan_buffer_cell_south ( .CLK_DR_OUT(clk_dr_south), .HI_Z_OUT(hiz_jtag_south), .MODE_OUT(mode_jtag_south), .RST_JTAG_OUT( rst_jtag_south), .SCAN_OUT(scan_in_south), .SHIFT_DR_OUT( shift_dr_south), .UPDATE_DR_OUT(update_dr_south), .CLK_DR_IN( clk_dr_west), .HI_Z_IN(hiz_jtag_west), .MODE_IN(mode_jtag_west), .RST_JTAG_IN(rst_jtag_west), .SCAN_IN(pad62_sout), .SHIFT_DR_IN( shift_dr_west), .UPDATE_DR_IN(update_dr_west) ); ipb_ph_ou_04_5t pad34 ( .ENB(1'b1), .IN0(1'b0) ); ipb_ph_bi_08_5t_s pad83 ( .ENB(pad83_en), .IN0(\pci_ad_out_jtag[21] ), .Y( \pci_ad_in[21] ), .PADPIN(PAD[21]) ); ipb_ph_bi_04_5t_s pad189 ( .ENB(pad189_en), .IN0(\la_out_jtag[16] ), .Y( \la_in_ah[16] ), .PADPIN(LA[16]) ); ipb_ph_bi_04_5t_s pad192 ( .ENB(pad192_en), .IN0(\la_out_jtag[19] ), .Y( \la_in_ah[19] ), .PADPIN(LA[19]) ); ipb_ph_bi_08_5t_s pad119 ( .ENB(pad119_en), .IN0(\pci_ad_out_jtag[4] ), .Y(\pci_ad_in[4] ), .PADPIN(PAD[4]) ); ipb_ph_bi_04_5t_s pad150 ( .ENB(pad150_en), .IN0(\ld_out_jtag[12] ), .Y( \ld_in_ah[12] ), .PADPIN(LD[12]) ); ipb_ph_in_5t_s pad229 ( .PADPIN(TS[12]), .Y(\ts_ah[12] ) ); bscan_cell pad5_jtag ( .PAD_IN(\ts_ah[0] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad5_sout), .SCAN_IN(pad4_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad164_jtag ( .PAD_OUT(pci_clk_jtag), .PAD_ENB(pad164_en), .PAD_IN(pci_clk_jtag), .CORE_ENBZ(lclke_rz), .CORE_IN(sysclk_c), .SCAN_OUT(pad164_sout), .SCAN_IN(pad162_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east ), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_east) ); bscan_cell pad244_jtag ( .PAD_OUT(\td_jtag_ah[14] ), .PAD_ENB(pad244_en), .PAD_IN(\td_jtag_ah[14] ), .CORE_ENBZ(1'b0), .CORE_IN(\td_ah[14] ), .SCAN_OUT(pad244_sout), .SCAN_IN(pad243_sout), .SHIFTDR(shift_dr_north ), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE( mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cell pad72_jtag ( .PAD_OUT(\pci_ad_out_jtag[30] ), .PAD_ENB(pad72_en ), .PAD_IN(\pci_ad_in[30] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN( \pci_ad_out[30] ), .SCAN_OUT(pad72_sout), .SCAN_IN(pad71_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pad_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad94_jtag ( .PAD_OUT(pci_irdy_out_jtag), .PAD_ENB(pad94_en), .PAD_IN(pci_irdy_in_l), .CORE_ENBZ(pci_irdy_en_l), .CORE_IN( pci_irdy_out_l), .SCAN_OUT(pad94_sout), .SCAN_IN(pirdy_cntl_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pirdy_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_in_5t_s pad18 ( .PADPIN(RS[2]), .Y(\rs_ah[2] ) ); ipb_ph_in_5t_s pad24 ( .PADPIN(RS[3]), .Y(\rs_ah[3] ) ); ipb_ph_in_5t_s pad41 ( .PADPIN(TS[4]), .Y(\ts_ah[4] ) ); ipb_ph_bi_04_5t_s pad177 ( .ENB(pad177_en), .IN0(\la_out_jtag[6] ), .Y( \la_in_ah[6] ), .PADPIN(LA[6]) ); ipb_ph_in_5t_s pad247 ( .PADPIN(RC[15]), .Y(\rc_ah[15] ) ); ipb_ph_in_5t_s pad66 ( .PADPIN(PCLK), .Y(pci_clk) ); bscan_cell pad56_jtag ( .PAD_OUT(\td_jtag_ah[6] ), .PAD_ENB(pad56_en), .PAD_IN(\td_jtag_ah[6] ), .CORE_ENBZ(1'b0), .CORE_IN(\td_ah[6] ), .SCAN_OUT(pad56_sout), .SCAN_IN(pad55_sout), .SHIFTDR(shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west ), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_bi_08_5t_s pad88 ( .ENB(pad88_en), .IN0(\pci_ad_out_jtag[16] ), .Y( \pci_ad_in[16] ), .PADPIN(PAD[16]) ); ipb_ph_bi_08_5t_s pad112 ( .ENB(pad112_en), .IN0(\pci_cbe_out_jtag[0] ), .Y(\pci_cbe_in_l[0] ), .PADPIN(PCBE[0]) ); ipb_ph_vs_all pad202_extra ( .GNDCORE(VSS) ); bscan_cell pad140_jtag ( .PAD_OUT(\ld_out_jtag[4] ), .PAD_ENB(pad140_en), .PAD_IN(\ld_in_ah[4] ), .CORE_ENBZ(ld_enlo_az), .CORE_IN( \ld_out_ah[4] ), .SCAN_OUT(pad140_sout), .SCAN_IN(pad139_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(ld_enlo_jtag), .HI_Z(hiz_jtag_east) ); bscan_cell pad213_jtag ( .PAD_IN(\rd_ah[10] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad213_sout), .SCAN_IN(pad212_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cell pad228_jtag ( .PAD_IN(\tc_ah[12] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad228_sout), .SCAN_IN(pad226_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_ou_04_5t pad222 ( .ENB(pad222_en), .IN0(\td_jtag_ah[11] ), .PADPIN( TD[11]) ); bscan_cell pad237_jtag ( .PAD_IN(\ts_ah[13] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad237_sout), .SCAN_IN(pad236_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cell pad117_jtag ( .PAD_OUT(\pci_ad_out_jtag[6] ), .PAD_ENB( pad117_en), .PAD_IN(\pci_ad_in[6] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN(\pci_ad_out[6] ), .SCAN_OUT(pad117_sout), .SCAN_IN( pad116_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL( pad_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_vs_all pad135 ( .GNDCORE(VSS) ); ipb_ph_in_5t_s pad205 ( .PADPIN(RD[9]), .Y(\rd_ah[9] ) ); ipb_ph_in_5t_s pad199 ( .PADPIN(TS[8]), .Y(\ts_ah[8] ) ); bscan_cell pad25_jtag ( .PAD_IN(\rd_ah[3] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad25_sout), .SCAN_IN(pad24_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cntl_cell pcbe1_cntl ( .SCAN_IN(pad101_sout), .SYS_LOGIC_CNTL( pci_cbe_en_l), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .SHIFTDR(shift_dr_south), .RESET(rst_jtag_south), .SCAN_OUT( pcbe1_cntl_sout), .DIR_CNTL(pcbe1_en_jtag) ); ipb_ph_vs_all pad182 ( .GNDCORE(VSS) ); bscan_cell pad108_jtag ( .PAD_OUT(\pci_ad_out_jtag[11] ), .PAD_ENB( pad108_en), .PAD_IN(\pci_ad_in[11] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN(\pci_ad_out[11] ), .SCAN_OUT(pad108_sout), .SCAN_IN( pad107_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL( pad_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_bi_08_5t_s pad76 ( .ENB(pad76_en), .IN0(\pci_ad_out_jtag[26] ), .Y( \pci_ad_in[26] ), .PADPIN(PAD[26]) ); ipb_ph_bi_08_5t_s pad93 ( .ENB(pad93_en), .IN0(pci_frame_out_jtag), .Y( pci_frame_in_l), .PADPIN(PFRAME) ); bscan_cell pad17_jtag ( .PAD_IN(\rc_ah[2] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad17_sout), .SCAN_IN(pad14_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_vd_all pad99_extra ( .VDDCORE(VDD) ); ipb_ph_bi_08_5t_s pad109 ( .ENB(pad109_en), .IN0(\pci_ad_out_jtag[10] ), .Y(\pci_ad_in[10] ), .PADPIN(PAD[10]) ); ipb_ph_bi_04_5t_s pad140 ( .ENB(pad140_en), .IN0(\ld_out_jtag[4] ), .Y( \ld_in_ah[4] ), .PADPIN(LD[4]) ); ipb_ph_vs_all pad167 ( .GNDCORE(VSS) ); ipb_ph_in_5t_s pad239 ( .PADPIN(RC[14]), .Y(\rc_ah[14] ) ); bscan_cell pad101_jtag ( .PAD_OUT(pci_par_out_jtag), .PAD_ENB(pad101_en), .PAD_IN(pci_par_in), .CORE_ENBZ(pci_par_en_l), .CORE_IN(pci_par_out), .SCAN_OUT(pad101_sout), .SCAN_IN(ppar_cntl_sout), .SHIFTDR( shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(ppar_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad221_jtag ( .PAD_IN(\ts_ah[11] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad221_sout), .SCAN_IN(pad220_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_in_5t_s pad2 ( .PADPIN(RS[0]), .Y(\rs_ah[0] ) ); ipb_ph_vd_all pad15_extra ( .VDDCORE(VDD) ); ipb_ph_in_5t_s pad51 ( .PADPIN(RC[6]), .Y(\rc_ah[6] ) ); ipb_ph_in_5t_s pad43 ( .PADPIN(RC[5]), .Y(\rc_ah[5] ) ); bscan_cell pad18_jtag ( .PAD_IN(\rs_ah[2] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad18_sout), .SCAN_IN(pad17_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad23_jtag ( .PAD_IN(\rc_ah[3] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad23_sout), .SCAN_IN(pad22_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad205_jtag ( .PAD_IN(\rd_ah[9] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad205_sout), .SCAN_IN(pad204_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_ou_04_5t pad64 ( .ENB(1'b1), .IN0(1'b0) ); ipb_ph_bi_08_5t_s pad81 ( .ENB(pad81_en), .IN0(\pci_ad_out_jtag[23] ), .Y( \pci_ad_in[23] ), .PADPIN(PAD[23]) ); ipb_ph_bi_04_5t_s pad152 ( .ENB(pad152_en), .IN0(\ld_out_jtag[14] ), .Y( \ld_in_ah[14] ), .PADPIN(LD[14]) ); ipb_ph_bi_04_5t_s pad175 ( .ENB(pad175_en), .IN0(\la_out_jtag[4] ), .Y( \la_in_ah[4] ), .PADPIN(LA[4]) ); ipb_ph_vd_all pad245 ( .VDDCORE(VDD) ); bscan_cntl_cell lwr_cntl ( .SCAN_IN(pad168_sout), .SYS_LOGIC_CNTL( lwr_en_rz), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .SHIFTDR(shift_dr_east), .RESET(rst_jtag_east), .SCAN_OUT( lwr_cntl_sout), .DIR_CNTL(lwr_en_jtag) ); bscan_cell pad111_jtag ( .PAD_OUT(\pci_ad_out_jtag[8] ), .PAD_ENB( pad111_en), .PAD_IN(\pci_ad_in[8] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN(\pci_ad_out[8] ), .SCAN_OUT(pad111_sout), .SCAN_IN( pad110_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL( pad_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_bi_04_5t_s pad190 ( .ENB(pad190_en), .IN0(\la_out_jtag[17] ), .Y( \la_in_ah[17] ), .PADPIN(LA[17]) ); ipb_ph_in_5t_s pad5 ( .PADPIN(TS[0]), .Y(\ts_ah[0] ) ); ipb_ph_in_5t_s pad11 ( .PADPIN(RD[1]), .Y(\rd_ah[1] ) ); bscan_cell pad203_jtag ( .PAD_IN(\rc_ah[9] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad203_sout), .SCAN_IN(pad200_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cell pad215_jtag ( .PAD_IN(\ts_ah[10] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad215_sout), .SCAN_IN(pad214_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cell pad238_jtag ( .PAD_OUT(\td_jtag_ah[13] ), .PAD_ENB(pad238_en), .PAD_IN(\td_jtag_ah[13] ), .CORE_ENBZ(1'b0), .CORE_IN(\td_ah[13] ), .SCAN_OUT(pad238_sout), .SCAN_IN(pad237_sout), .SHIFTDR(shift_dr_north ), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE( mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_in_5t_s pad36 ( .PADPIN(RC[4]), .Y(\rc_ah[4] ) ); bscan_cntl_cell lrd_cntl ( .SCAN_IN(pad169_sout), .SYS_LOGIC_CNTL( lrd_en_rz), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .SHIFTDR(shift_dr_east), .RESET(rst_jtag_east), .SCAN_OUT( lrd_cntl_sout), .DIR_CNTL(lrd_en_jtag) ); jtag_top jtag_top ( .TMS(jtms_ah), .TCK(jtclk_c), .TDI(jtdi_ah), .TRST( jtrst_ah), .TDO(jtdo_ah), .TDO_ENB(jtdo_en), .SHIFTDR(shift_dr), .UPDATEDR(update_dr), .CLOCKDR(clk_dr), .RESET(rst_jtag), .MODE( mode_jtag), .HI_Z(hiz_jtag), .SO_BS(so_bs) ); ipb_ph_ou_04_5t pad230 ( .ENB(pad230_en), .IN0(\td_jtag_ah[12] ), .PADPIN( TD[12]) ); ipb_ph_ou_04_5t pad127 ( .ENB(pad127_en), .IN0(pcix_ds_jtag), .PADPIN(PXDS ) ); ipb_ph_bi_04_5t_s_od pad100 ( .ENB(pad100_en), .IN0(pci_serr_jtag), .PADPIN(PSERR) ); ipb_ph_bi_04_5t_s pad149 ( .ENB(pad149_en), .IN0(\ld_out_jtag[11] ), .Y( \ld_in_ah[11] ), .PADPIN(LD[11]) ); ipb_ph_in_5t_s pad217 ( .PADPIN(RC[11]), .Y(\rc_ah[11] ) ); ipb_ph_vs_all pad16 ( .GNDCORE(VSS) ); ipb_ph_in_5t_s pad58 ( .PADPIN(RS[7]), .Y(\rs_ah[7] ) ); bscan_cell pad11_jtag ( .PAD_IN(\rd_ah[1] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad11_sout), .SCAN_IN(pad10_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad107_jtag ( .PAD_OUT(\pci_ad_out_jtag[12] ), .PAD_ENB( pad107_en), .PAD_IN(\pci_ad_in[12] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN(\pci_ad_out[12] ), .SCAN_OUT(pad107_sout), .SCAN_IN( pad106_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL( pad_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_bi_08_5t_s pad78 ( .ENB(pad78_en), .IN0(\pci_ad_out_jtag[24] ), .Y( \pci_ad_in[24] ), .PADPIN(PAD[24]) ); ipb_ph_vs_all pad231_extra ( .GNDCORE(VSS) ); ipb_ph_bi_04_5t_s pad169 ( .ENB(pad169_en), .IN0(lwr_out_jtag), .Y( lwr_in_az), .PADPIN(LWR) ); bscan_cell pad118_jtag ( .PAD_OUT(\pci_ad_out_jtag[5] ), .PAD_ENB( pad118_en), .PAD_IN(\pci_ad_in[5] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN(\pci_ad_out[5] ), .SCAN_OUT(pad118_sout), .SCAN_IN( pad117_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL( pad_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad123_jtag ( .PAD_OUT(\pci_ad_out_jtag[0] ), .PAD_ENB( pad123_en), .PAD_IN(\pci_ad_in[0] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN(\pci_ad_out[0] ), .SCAN_OUT(pad123_sout), .SCAN_IN( pad122_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL( pad_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad236_jtag ( .PAD_IN(\tc_ah[13] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad236_sout), .SCAN_IN(pad235_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cntl_cell ld_cntllo ( .SCAN_IN(scan_in_east), .SYS_LOGIC_CNTL( ld_enlo_az), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .SHIFTDR(shift_dr_east), .RESET(rst_jtag_east), .SCAN_OUT(ld_cntl_sout ), .DIR_CNTL(ld_enlo_jtag) ); bscan_cell pad212_jtag ( .PAD_IN(\rs_ah[10] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad212_sout), .SCAN_IN(pad211_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cell pad229_jtag ( .PAD_IN(\ts_ah[12] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad229_sout), .SCAN_IN(pad228_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cntl_cell pcbe0_cntl ( .SCAN_IN(pad111_sout), .SYS_LOGIC_CNTL( pci_cbe_en_l), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .SHIFTDR(shift_dr_south), .RESET(rst_jtag_south), .SCAN_OUT( pcbe0_cntl_sout), .DIR_CNTL(pcbe0_en_jtag) ); bscan_cell pad109_jtag ( .PAD_OUT(\pci_ad_out_jtag[10] ), .PAD_ENB( pad109_en), .PAD_IN(\pci_ad_in[10] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN(\pci_ad_out[10] ), .SCAN_OUT(pad109_sout), .SCAN_IN( pad108_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL( pad_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_ou_04_5t pad31 ( .ENB(1'b1), .IN0(1'b0) ); ipb_ph_bi_08_5t_s pad86 ( .ENB(pad86_en), .IN0(\pci_ad_out_jtag[18] ), .Y( \pci_ad_in[18] ), .PADPIN(PAD[18]) ); ipb_ph_bi_08_5t_s pad107 ( .ENB(pad107_en), .IN0(\pci_ad_out_jtag[12] ), .Y(\pci_ad_in[12] ), .PADPIN(PAD[12]) ); ipb_ph_bi_08_5t_s pad120 ( .ENB(pad120_en), .IN0(\pci_ad_out_jtag[3] ), .Y(\pci_ad_in[3] ), .PADPIN(PAD[3]) ); ipb_ph_vs_all pad210 ( .GNDCORE(VSS) ); bscan_cell pad24_jtag ( .PAD_IN(\rs_ah[3] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad24_sout), .SCAN_IN(pad23_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_vd_all pad134_extra ( .VDDCORE(VDD) ); bscan_cell pad116_jtag ( .PAD_OUT(\pci_ad_out_jtag[7] ), .PAD_ENB( pad116_en), .PAD_IN(\pci_ad_in[7] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN(\pci_ad_out[7] ), .SCAN_OUT(pad116_sout), .SCAN_IN( pad112_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL( pad_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_in_5t_s pad237 ( .PADPIN(TS[13]), .Y(\ts_ah[13] ) ); bscan_cell pad100_jtag ( .PAD_OUT(pci_serr_jtag), .PAD_ENB(pad100_en), .PAD_IN(pci_serr_jtag), .CORE_ENBZ(1'b0), .CORE_IN(pci_serr_l), .SCAN_OUT(pad100_sout), .SCAN_IN(pad98_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE( mode_jtag_south), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_south) ); ipb_ph_in_5t_s pad44 ( .PADPIN(RS[5]), .Y(\rs_ah[5] ) ); ipb_ph_in_5t_s pad197 ( .PADPIN(RD[8]), .Y(\rd_ah[8] ) ); bscan_cell pad124_jtag ( .PAD_OUT(pinta_out_jtag), .PAD_ENB(pad124_en), .PAD_IN(pinta_out_jtag), .CORE_ENBZ(1'b0), .CORE_IN(lint_out_rz), .SCAN_OUT(pad124_sout), .SCAN_IN(pad123_sout), .SHIFTDR(shift_dr_south ), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE( mode_jtag_south), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_south) ); ipb_ph_ou_04_5t pad56 ( .ENB(pad56_en), .IN0(\td_jtag_ah[6] ), .PADPIN(TD [6]) ); ipb_ph_in_5t_s pad155 ( .PADPIN(LMS), .Y(lms_ah) ); bscan_cell pad204_jtag ( .PAD_IN(\rs_ah[9] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad204_sout), .SCAN_IN(pad203_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_ou_04_5t pad63 ( .ENB(1'b1), .IN0(1'b0) ); ipb_ph_bi_04_5t_s pad172 ( .ENB(pad172_en), .IN0(\la_out_jtag[1] ), .Y( \la_in_ah[1] ), .PADPIN(LA[1]) ); ipb_ph_in_5t_s pad242 ( .PADPIN(TC[14]), .Y(\tc_ah[14] ) ); bscan_cell pad220_jtag ( .PAD_IN(\tc_ah[11] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad220_sout), .SCAN_IN(pad219_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_bi_04_5t_s pad147 ( .ENB(pad147_en), .IN0(\ld_out_jtag[9] ), .Y( \ld_in_ah[9] ), .PADPIN(LD[9]) ); bscan_cell pad110_jtag ( .PAD_OUT(\pci_ad_out_jtag[9] ), .PAD_ENB( pad110_en), .PAD_IN(\pci_ad_in[9] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN(\pci_ad_out[9] ), .SCAN_OUT(pad110_sout), .SCAN_IN( pad109_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL( pad_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_bi_04_5t_s_od pad160 ( .ENB(pad160_en), .IN0(lint_out_jtag), .Y( lint_in_az), .PADPIN(LINT) ); ipb_ph_in_5t_s pad250 ( .PADPIN(TC[15]), .Y(\tc_ah[15] ) ); ipb_ph_vd_all pad69_extra ( .VDDCORE(VDD) ); bscan_cell pad19_jtag ( .PAD_IN(\rd_ah[2] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad19_sout), .SCAN_IN(pad18_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_in_5t_s pad23 ( .PADPIN(RC[3]), .Y(\rc_ah[3] ) ); ipb_ph_in_5t_s pad38 ( .PADPIN(RD[4]), .Y(\rd_ah[4] ) ); ipb_ph_bi_08_5t_s pad71 ( .ENB(pad71_en), .IN0(\pci_ad_out_jtag[31] ), .Y( \pci_ad_in[31] ), .PADPIN(PAD[31]) ); bscan_cell pad22_jtag ( .PAD_OUT(\td_jtag_ah[2] ), .PAD_ENB(pad22_en), .PAD_IN(\td_jtag_ah[2] ), .CORE_ENBZ(1'b0), .CORE_IN(\td_ah[2] ), .SCAN_OUT(pad22_sout), .SCAN_IN(pad21_sout), .SHIFTDR(shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west ), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_bi_04_5t_s pad185 ( .ENB(pad185_en), .IN0(\la_out_jtag[12] ), .Y( \la_in_ah[12] ), .PADPIN(LA[12]) ); bscan_cell pad214_jtag ( .PAD_IN(\tc_ah[10] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad214_sout), .SCAN_IN(pad213_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_bi_08_5t_s pad94 ( .ENB(pad94_en), .IN0(pci_irdy_out_jtag), .Y( pci_irdy_in_l), .PADPIN(PIRDY) ); bscan_cntl_cell pperr_cntl ( .SCAN_IN(pad97_sout), .SYS_LOGIC_CNTL( pci_perr_en_l), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .SHIFTDR(shift_dr_south), .RESET(rst_jtag_south), .SCAN_OUT( pperr_cntl_sout), .DIR_CNTL(pperr_en_jtag) ); ipb_ph_vs_all pad115 ( .GNDCORE(VSS) ); ipb_ph_bi_04_5t_s_up pad129 ( .ENB(1'b1), .IN0(1'b0), .Y(jtms_ah), .PADPIN(JTMS) ); ipb_ph_bi_04_5t_s_up pad132 ( .ENB(1'b1), .IN0(1'b0), .Y(jtdi_ah), .PADPIN(JTDI) ); ipb_ph_vs_all pad202 ( .GNDCORE(VSS) ); ipb_ph_in_5t_s pad219 ( .PADPIN(RD[11]), .Y(\rd_ah[11] ) ); bscan_cell pad230_jtag ( .PAD_OUT(\td_jtag_ah[12] ), .PAD_ENB(pad230_en), .PAD_IN(\td_jtag_ah[12] ), .CORE_ENBZ(1'b0), .CORE_IN(\td_ah[12] ), .SCAN_OUT(pad230_sout), .SCAN_IN(pad229_sout), .SHIFTDR(shift_dr_north ), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE( mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cell pad226_jtag ( .PAD_IN(\rd_ah[12] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad226_sout), .SCAN_IN(pad225_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_in_5t_s pad225 ( .PADPIN(RS[12]), .Y(\rs_ah[12] ) ); ipb_ph_vs_all pad256_extra ( .GNDCORE(VSS) ); bscan_cell pad119_jtag ( .PAD_OUT(\pci_ad_out_jtag[4] ), .PAD_ENB( pad119_en), .PAD_IN(\pci_ad_in[4] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN(\pci_ad_out[4] ), .SCAN_OUT(pad119_sout), .SCAN_IN( pad118_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL( pad_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad239_jtag ( .PAD_IN(\rc_ah[14] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad239_sout), .SCAN_IN(pad238_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cell pad122_jtag ( .PAD_OUT(\pci_ad_out_jtag[1] ), .PAD_ENB( pad122_en), .PAD_IN(\pci_ad_in[1] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN(\pci_ad_out[1] ), .SCAN_OUT(pad122_sout), .SCAN_IN( pad121_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL( pad_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_in_5t_s pad45 ( .PADPIN(RD[5]), .Y(\rd_ah[5] ) ); ipb_ph_vs_all pad135_extra ( .GNDCORE(VSS) ); bscan_cell pad10_jtag ( .PAD_IN(\rs_ah[1] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad10_sout), .SCAN_IN(pad9_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad106_jtag ( .PAD_OUT(\pci_ad_out_jtag[13] ), .PAD_ENB( pad106_en), .PAD_IN(\pci_ad_in[13] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN(\pci_ad_out[13] ), .SCAN_OUT(pad106_sout), .SCAN_IN( pad105_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL( pad_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_in_5t_s pad3 ( .PADPIN(RD[0]), .Y(\rd_ah[0] ) ); ipb_ph_in_5t_s pad4 ( .PADPIN(TC[0]), .Y(\tc_ah[0] ) ); ipb_ph_ou_04_5t pad62 ( .ENB(pad62_en), .IN0(\td_jtag_ah[7] ), .PADPIN(TD [7]) ); bscan_cell pad1_jtag ( .PAD_IN(\rc_ah[0] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad1_sout), .SCAN_IN(scan_in_west), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad240_jtag ( .PAD_IN(\rs_ah[14] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad240_sout), .SCAN_IN(pad239_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_bi_08_5t_s pad87 ( .ENB(pad87_en), .IN0(\pci_ad_out_jtag[17] ), .Y( \pci_ad_in[17] ), .PADPIN(PAD[17]) ); ipb_ph_in_5t_s pad154 ( .PADPIN(LIM), .Y(lim_ah) ); ipb_ph_bi_04_5t_s pad173 ( .ENB(pad173_en), .IN0(\la_out_jtag[2] ), .Y( \la_in_ah[2] ), .PADPIN(LA[2]) ); ipb_ph_in_5t_s pad243 ( .PADPIN(TS[14]), .Y(\ts_ah[14] ) ); ipb_ph_vd_all pad245_extra ( .VDDCORE(VDD) ); ipb_ph_vs_all pad182_extra ( .GNDCORE(VSS) ); ipb_ph_vd_all pad114_extra ( .VDDCORE(VDD) ); bscan_cell pad52_jtag ( .PAD_IN(\rs_ah[6] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad52_sout), .SCAN_IN(pad51_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad199_jtag ( .PAD_IN(\ts_ah[8] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad199_sout), .SCAN_IN(pad198_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cell pad160_jtag ( .PAD_OUT(lint_out_jtag), .PAD_ENB(pad160_en), .PAD_IN(lint_in_az), .CORE_ENBZ(lms_az), .CORE_IN(lint_out_rz), .SCAN_OUT(pad160_sout), .SCAN_IN(lint_cntl_sout), .SHIFTDR( shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(lint_en_jtag), .HI_Z(hiz_jtag_east) ); ipb_ph_in_5t_s pad17 ( .PADPIN(RC[2]), .Y(\rc_ah[2] ) ); bscan_buffer_cell bscan_buffer_cell_north ( .CLK_DR_OUT(clk_dr_north), .HI_Z_OUT(hiz_jtag_north), .MODE_OUT(mode_jtag_north), .RST_JTAG_OUT( rst_jtag_north), .SCAN_OUT(scan_in_north), .SHIFT_DR_OUT( shift_dr_north), .UPDATE_DR_OUT(update_dr_north), .CLK_DR_IN( clk_dr_east), .HI_Z_IN(hiz_jtag_east), .MODE_IN(mode_jtag_east), .RST_JTAG_IN(rst_jtag_east), .SCAN_IN(pad192_sout), .SHIFT_DR_IN( shift_dr_east), .UPDATE_DR_IN(update_dr_east) ); ipb_ph_in_5t_s pad196 ( .PADPIN(RS[8]), .Y(\rs_ah[8] ) ); bscan_cell pad60_jtag ( .PAD_IN(\tc_ah[7] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad60_sout), .SCAN_IN(pad59_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad76_jtag ( .PAD_OUT(\pci_ad_out_jtag[26] ), .PAD_ENB(pad76_en ), .PAD_IN(\pci_ad_in[26] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN( \pci_ad_out[26] ), .SCAN_OUT(pad76_sout), .SCAN_IN(pad75_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pad_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad186_jtag ( .PAD_OUT(\la_out_jtag[13] ), .PAD_ENB(pad186_en), .PAD_IN(\la_in_ah[13] ), .CORE_ENBZ(la_en_rz), .CORE_IN( \la_out_rh[13] ), .SCAN_OUT(pad186_sout), .SCAN_IN(pad185_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(la_en_jtag), .HI_Z( hiz_jtag_east) ); bscan_cell pad176_jtag ( .PAD_OUT(\la_out_jtag[5] ), .PAD_ENB(pad176_en), .PAD_IN(\la_in_ah[5] ), .CORE_ENBZ(la_en_rz), .CORE_IN(\la_out_rh[5] ), .SCAN_OUT(pad176_sout), .SCAN_IN(pad175_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east ), .DIR_CNTL(la_en_jtag), .HI_Z(hiz_jtag_east) ); bscan_cell pad190_jtag ( .PAD_OUT(\la_out_jtag[17] ), .PAD_ENB(pad190_en), .PAD_IN(\la_in_ah[17] ), .CORE_ENBZ(la_en_rz), .CORE_IN( \la_out_rh[17] ), .SCAN_OUT(pad190_sout), .SCAN_IN(pad189_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(la_en_jtag), .HI_Z( hiz_jtag_east) ); ipb_ph_ou_04_5t pad30 ( .ENB(1'b1), .IN0(1'b0) ); ipb_ph_in_5t_s pad19 ( .PADPIN(RD[2]), .Y(\rd_ah[2] ) ); ipb_ph_ou_04_5t pad22 ( .ENB(pad22_en), .IN0(\td_jtag_ah[2] ), .PADPIN(TD [2]) ); bscan_cntl_cell pirdy_cntl ( .SCAN_IN(pad93_sout), .SYS_LOGIC_CNTL( pci_irdy_en_l), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .SHIFTDR(shift_dr_south), .RESET(rst_jtag_south), .SCAN_OUT( pirdy_cntl_sout), .DIR_CNTL(pirdy_en_jtag) ); bscan_cntl_cell la_cntl ( .SCAN_IN(pad170_sout), .SYS_LOGIC_CNTL(la_en_rz), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .SHIFTDR( shift_dr_east), .RESET(rst_jtag_east), .SCAN_OUT(la_cntl_sout), .DIR_CNTL(la_en_jtag) ); bscan_cell pad86_jtag ( .PAD_OUT(\pci_ad_out_jtag[18] ), .PAD_ENB(pad86_en ), .PAD_IN(\pci_ad_in[18] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN( \pci_ad_out[18] ), .SCAN_OUT(pad86_sout), .SCAN_IN(pad85_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pad_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_bi_08_5t_s pad106 ( .ENB(pad106_en), .IN0(\pci_ad_out_jtag[13] ), .Y(\pci_ad_in[13] ), .PADPIN(PAD[13]) ); ipb_ph_bi_08_5t_s pad121 ( .ENB(pad121_en), .IN0(\pci_ad_out_jtag[2] ), .Y(\pci_ad_in[2] ), .PADPIN(PAD[2]) ); ipb_ph_in_5t_s pad211 ( .PADPIN(RC[10]), .Y(\rc_ah[10] ) ); bscan_cell pad169_jtag ( .PAD_OUT(lwr_out_jtag), .PAD_ENB(pad169_en), .PAD_IN(lwr_in_az), .CORE_ENBZ(lwr_en_rz), .CORE_IN(lwr_out_rz), .SCAN_OUT(pad169_sout), .SCAN_IN(lwr_cntl_sout), .SHIFTDR( shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(lwr_en_jtag), .HI_Z(hiz_jtag_east) ); bscan_cell pad152_jtag ( .PAD_OUT(\ld_out_jtag[14] ), .PAD_ENB(pad152_en), .PAD_IN(\ld_in_ah[14] ), .CORE_ENBZ(ld_enhi_az), .CORE_IN( \ld_out_ah[14] ), .SCAN_OUT(pad152_sout), .SCAN_IN(pad151_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(ld_enlo_jtag), .HI_Z(hiz_jtag_east) ); ipb_ph_vd_all pad49_extra ( .VDDCORE(VDD) ); ipb_ph_bi_08_5t_s pad79 ( .ENB(pad79_en), .IN0(\pci_cbe_out_jtag[3] ), .Y( \pci_cbe_in_l[3] ), .PADPIN(PCBE[3]) ); ipb_ph_ou_04_5t pad168 ( .ENB(pad168_en), .IN0(lbhe_jtag), .PADPIN(LBHE) ); ipb_ph_in_5t_s pad236 ( .PADPIN(TC[13]), .Y(\tc_ah[13] ) ); bscan_cell pad44_jtag ( .PAD_IN(\rs_ah[5] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad44_sout), .SCAN_IN(pad43_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad249_jtag ( .PAD_IN(\rd_ah[15] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad249_sout), .SCAN_IN(pad248_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cell pad96_jtag ( .PAD_OUT(pci_devsel_out_jtag), .PAD_ENB(pad96_en), .PAD_IN(pci_devsel_in_l), .CORE_ENBZ(pci_trgt_en_l), .CORE_IN( pci_devsel_out_l), .SCAN_OUT(pad96_sout), .SCAN_IN(pdevsel_cntl_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pdevsel_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad180_jtag ( .PAD_OUT(\la_out_jtag[9] ), .PAD_ENB(pad180_en), .PAD_IN(\la_in_ah[9] ), .CORE_ENBZ(la_en_rz), .CORE_IN(\la_out_rh[9] ), .SCAN_OUT(pad180_sout), .SCAN_IN(pad179_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east ), .DIR_CNTL(la_en_jtag), .HI_Z(hiz_jtag_east) ); bscan_cell pad179_jtag ( .PAD_OUT(\la_out_jtag[8] ), .PAD_ENB(pad179_en), .PAD_IN(\la_in_ah[8] ), .CORE_ENBZ(la_en_rz), .CORE_IN(\la_out_rh[8] ), .SCAN_OUT(pad179_sout), .SCAN_IN(pad178_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east ), .DIR_CNTL(la_en_jtag), .HI_Z(hiz_jtag_east) ); ipb_ph_vd_all pad114 ( .VDDCORE(VDD) ); ipb_ph_ou_04_5t pad133 ( .ENB(jtdo_en), .IN0(jtdo_ah), .PADPIN(JTDO) ); ipb_ph_in_5t_s pad203 ( .PADPIN(RC[9]), .Y(\rc_ah[9] ) ); bscan_cell pad54_jtag ( .PAD_IN(\tc_ah[6] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad54_sout), .SCAN_IN(pad53_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad142_jtag ( .PAD_OUT(\ld_out_jtag[6] ), .PAD_ENB(pad142_en), .PAD_IN(\ld_in_ah[6] ), .CORE_ENBZ(ld_enlo_az), .CORE_IN( \ld_out_ah[6] ), .SCAN_OUT(pad142_sout), .SCAN_IN(pad141_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(ld_enlo_jtag), .HI_Z(hiz_jtag_east) ); ipb_ph_in_5t_s pad224 ( .PADPIN(RC[12]), .Y(\rc_ah[12] ) ); ipb_ph_vs_all pad39 ( .GNDCORE(VSS) ); ipb_ph_bi_04_5t_s pad184 ( .ENB(pad184_en), .IN0(\la_out_jtag[11] ), .Y( \la_in_ah[11] ), .PADPIN(LA[11]) ); ipb_ph_bi_08_5t_s pad95 ( .ENB(pad95_en), .IN0(pci_trdy_out_jtag), .Y( pci_trdy_in_l), .PADPIN(PTRDY) ); bscan_cell pad250_jtag ( .PAD_IN(\tc_ah[15] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad250_sout), .SCAN_IN(pad249_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_ou_04_5t pad128 ( .ENB(pad128_en), .IN0(pcix_blast_jtag), .PADPIN( PXBLAST) ); ipb_ph_in_5t_s pad218 ( .PADPIN(RS[11]), .Y(\rs_ah[11] ) ); ipb_ph_bi_04_5t_s pad146 ( .ENB(pad146_en), .IN0(\ld_out_jtag[8] ), .Y( \ld_in_ah[8] ), .PADPIN(LD[8]) ); bscan_cell pad79_jtag ( .PAD_OUT(\pci_cbe_out_jtag[3] ), .PAD_ENB(pad79_en ), .PAD_IN(\pci_cbe_in_l[3] ), .CORE_ENBZ(pci_cbe_en_l), .CORE_IN( \pci_cbe_out_l[3] ), .SCAN_OUT(pad79_sout), .SCAN_IN(pcbe3_cntl_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pcbe3_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_vs_all pad50 ( .GNDCORE(VSS) ); ipb_ph_in_5t_s pad57 ( .PADPIN(RC[7]), .Y(\rc_ah[7] ) ); ipb_ph_vs_all pad115_extra ( .GNDCORE(VSS) ); ipb_ph_in_5t_s pad251 ( .PADPIN(TS[15]), .Y(\ts_ah[15] ) ); bscan_cell pad42_jtag ( .PAD_OUT(\td_jtag_ah[4] ), .PAD_ENB(pad42_en), .PAD_IN(\td_jtag_ah[4] ), .CORE_ENBZ(1'b0), .CORE_IN(\td_ah[4] ), .SCAN_OUT(pad42_sout), .SCAN_IN(pad41_sout), .SHIFTDR(shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west ), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad189_jtag ( .PAD_OUT(\la_out_jtag[16] ), .PAD_ENB(pad189_en), .PAD_IN(\la_in_ah[16] ), .CORE_ENBZ(la_en_rz), .CORE_IN( \la_out_rh[16] ), .SCAN_OUT(pad189_sout), .SCAN_IN(pad188_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(la_en_jtag), .HI_Z( hiz_jtag_east) ); ipb_ph_in_5t_s pad161 ( .PADPIN(LCS), .Y(lcs_az) ); bscan_cell pad154_jtag ( .PAD_IN(lim_ah), .CORE_ENBZ(1'b0), .CORE_IN(1'b0), .SCAN_OUT(pad154_sout), .SCAN_IN(pad153_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east ), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_east) ); ipb_ph_vs_all pad70 ( .GNDCORE(VSS) ); bscan_cell pad66_jtag ( .PAD_IN(pci_clk), .CORE_ENBZ(1'b0), .CORE_IN(1'b0), .SCAN_OUT(pad66_sout), .SCAN_IN(pad65_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE( mode_jtag_south), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_south) ); bscan_cell pad80_jtag ( .PAD_IN(pci_idsel), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad80_sout), .SCAN_IN(pad79_sout), .SHIFTDR( shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_south) ); bscan_cell pad170_jtag ( .PAD_OUT(lrd_out_jtag), .PAD_ENB(pad170_en), .PAD_IN(lrd_in_az), .CORE_ENBZ(lrd_en_rz), .CORE_IN(lrd_out_rz), .SCAN_OUT(pad170_sout), .SCAN_IN(lrd_cntl_sout), .SHIFTDR( shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(lrd_en_jtag), .HI_Z(hiz_jtag_east) ); bscan_cell pad196_jtag ( .PAD_IN(\rs_ah[8] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad196_sout), .SCAN_IN(pad195_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_bi_08_5t_s pad77 ( .ENB(pad77_en), .IN0(\pci_ad_out_jtag[25] ), .Y( \pci_ad_in[25] ), .PADPIN(PAD[25]) ); ipb_ph_bi_04_5t_s pad141 ( .ENB(pad141_en), .IN0(\ld_out_jtag[5] ), .Y( \ld_in_ah[5] ), .PADPIN(LD[5]) ); ipb_ph_vs_all pad256 ( .GNDCORE(VSS) ); ipb_ph_ou_04_5t pad166 ( .ENB(1'b1), .IN0(1'b0) ); bscan_cell pad241_jtag ( .PAD_IN(\rd_ah[14] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad241_sout), .SCAN_IN(pad240_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_bi_04_5t_s pad183 ( .ENB(pad183_en), .IN0(\la_out_jtag[10] ), .Y( \la_in_ah[10] ), .PADPIN(LA[10]) ); bscan_cell pad77_jtag ( .PAD_OUT(\pci_ad_out_jtag[25] ), .PAD_ENB(pad77_en ), .PAD_IN(\pci_ad_in[25] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN( \pci_ad_out[25] ), .SCAN_OUT(pad77_sout), .SCAN_IN(pad76_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pad_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad187_jtag ( .PAD_OUT(\la_out_jtag[14] ), .PAD_ENB(pad187_en), .PAD_IN(\la_in_ah[14] ), .CORE_ENBZ(la_en_rz), .CORE_IN( \la_out_rh[14] ), .SCAN_OUT(pad187_sout), .SCAN_IN(pad186_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(la_en_jtag), .HI_Z( hiz_jtag_east) ); ipb_ph_in_5t_s pad25 ( .PADPIN(RD[3]), .Y(\rd_ah[3] ) ); ipb_ph_bi_08_5t_s pad92 ( .ENB(pad92_en), .IN0(\pci_cbe_out_jtag[2] ), .Y( \pci_cbe_in_l[2] ), .PADPIN(PCBE[2]) ); ipb_ph_vs_all pad210_extra ( .GNDCORE(VSS) ); bscan_cell pad161_jtag ( .PAD_IN(lcs_az), .CORE_ENBZ(1'b0), .CORE_IN(1'b0), .SCAN_OUT(pad161_sout), .SCAN_IN(pad160_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east ), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_east) ); ipb_ph_bi_08_5t_s pad108 ( .ENB(pad108_en), .IN0(\pci_ad_out_jtag[11] ), .Y(\pci_ad_in[11] ), .PADPIN(PAD[11]) ); ipb_ph_ou_04_5t pad238 ( .ENB(pad238_en), .IN0(\td_jtag_ah[13] ), .PADPIN( TD[13]) ); bscan_cell pad53_jtag ( .PAD_IN(\rd_ah[6] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad53_sout), .SCAN_IN(pad52_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad198_jtag ( .PAD_IN(\tc_ah[8] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad198_sout), .SCAN_IN(pad197_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_vd_all pad89 ( .VDDCORE(VDD) ); bscan_cell pad45_jtag ( .PAD_IN(\rd_ah[5] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad45_sout), .SCAN_IN(pad44_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad68_jtag ( .PAD_OUT(pci_req_jtag), .PAD_ENB(preq_en), .PAD_IN(pci_req_jtag), .CORE_ENBZ(pci_rstz), .CORE_IN(pci_req_l), .SCAN_OUT(pad68_sout), .SCAN_IN(pad67_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE( mode_jtag_south), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_south) ); ipb_ph_ou_04_5t pad223 ( .ENB(1'b1), .IN0(1'b0) ); ipb_ph_ou_04_5t pad113 ( .ENB(1'b1), .IN0(1'b0) ); ipb_ph_vd_all pad134 ( .VDDCORE(VDD) ); ipb_ph_in_5t_s pad204 ( .PADPIN(RS[9]), .Y(\rs_ah[9] ) ); bscan_cell pad98_jtag ( .PAD_OUT(pci_perr_out_jtag), .PAD_ENB(pad98_en), .PAD_IN(pci_perr_in_l), .CORE_ENBZ(pci_perr_en_l), .CORE_IN( pci_perr_out_l), .SCAN_OUT(pad98_sout), .SCAN_IN(pperr_cntl_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pperr_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad153_jtag ( .PAD_OUT(\ld_out_jtag[15] ), .PAD_ENB(pad153_en), .PAD_IN(\ld_in_ah[15] ), .CORE_ENBZ(ld_enhi_az), .CORE_IN( \ld_out_ah[15] ), .SCAN_OUT(pad153_sout), .SCAN_IN(pad152_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(ld_enlo_jtag), .HI_Z(hiz_jtag_east) ); ipb_ph_in_5t_s pad198 ( .PADPIN(TC[8]), .Y(\tc_ah[8] ) ); bscan_cell pad87_jtag ( .PAD_OUT(\pci_ad_out_jtag[17] ), .PAD_ENB(pad87_en ), .PAD_IN(\pci_ad_in[17] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN( \pci_ad_out[17] ), .SCAN_OUT(pad87_sout), .SCAN_IN(pad86_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pad_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad168_jtag ( .PAD_OUT(lbhe_jtag), .PAD_ENB(pad168_en), .PAD_IN(lbhe_jtag), .CORE_ENBZ(lbhe_en_rz), .CORE_IN(lbhe_rz), .SCAN_OUT(pad168_sout), .SCAN_IN(pad164_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east ), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_east) ); bscan_cell pad177_jtag ( .PAD_OUT(\la_out_jtag[6] ), .PAD_ENB(pad177_en), .PAD_IN(\la_in_ah[6] ), .CORE_ENBZ(la_en_rz), .CORE_IN(\la_out_rh[6] ), .SCAN_OUT(pad177_sout), .SCAN_IN(pad176_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east ), .DIR_CNTL(la_en_jtag), .HI_Z(hiz_jtag_east) ); bscan_cell pad191_jtag ( .PAD_OUT(\la_out_jtag[18] ), .PAD_ENB(pad191_en), .PAD_IN(\la_in_ah[18] ), .CORE_ENBZ(la_en_rz), .CORE_IN( \la_out_rh[18] ), .SCAN_OUT(pad191_sout), .SCAN_IN(pad190_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(la_en_jtag), .HI_Z( hiz_jtag_east) ); ipb_ph_vs_all pad90_extra ( .GNDCORE(VSS) ); bscan_buffer_cell bscan_buffer_cell_east ( .CLK_DR_OUT(clk_dr_east), .HI_Z_OUT(hiz_jtag_east), .MODE_OUT(mode_jtag_east), .RST_JTAG_OUT( rst_jtag_east), .SCAN_OUT(scan_in_east), .SHIFT_DR_OUT(shift_dr_east), .UPDATE_DR_OUT(update_dr_east), .CLK_DR_IN(clk_dr), .HI_Z_IN(hiz_jtag), .MODE_IN(mode_jtag), .RST_JTAG_IN(rst_jtag), .SCAN_IN(jtdi_ah), .SHIFT_DR_IN(shift_dr), .UPDATE_DR_IN(update_dr) ); ipb_ph_vs_all pad167_extra ( .GNDCORE(VSS) ); bscan_cell pad61_jtag ( .PAD_IN(\ts_ah[7] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad61_sout), .SCAN_IN(pad60_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); ipb_ph_in_5t_s pad59 ( .PADPIN(RD[7]), .Y(\rd_ah[7] ) ); ipb_ph_bi_04_5t_s pad148 ( .ENB(pad148_en), .IN0(\ld_out_jtag[10] ), .Y( \ld_in_ah[10] ), .PADPIN(LD[10]) ); bscan_cell pad9_jtag ( .PAD_IN(\rc_ah[1] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad9_sout), .SCAN_IN(pad6_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad248_jtag ( .PAD_IN(\rs_ah[15] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad248_sout), .SCAN_IN(pad247_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cell pad55_jtag ( .PAD_IN(\ts_ah[6] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad55_sout), .SCAN_IN(pad54_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cntl_cell pdevsel_cntl ( .SCAN_IN(pad95_sout), .SYS_LOGIC_CNTL( pci_trgt_en_l), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .SHIFTDR(shift_dr_south), .RESET(rst_jtag_south), .SCAN_OUT( pdevsel_cntl_sout), .DIR_CNTL(pdevsel_en_jtag) ); bscan_cell pad88_jtag ( .PAD_OUT(\pci_ad_out_jtag[16] ), .PAD_ENB(pad88_en ), .PAD_IN(\pci_ad_in[16] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN( \pci_ad_out[16] ), .SCAN_OUT(pad88_sout), .SCAN_IN(pad87_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pad_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad143_jtag ( .PAD_OUT(\ld_out_jtag[7] ), .PAD_ENB(pad143_en), .PAD_IN(\ld_in_ah[7] ), .CORE_ENBZ(ld_enlo_az), .CORE_IN( \ld_out_ah[7] ), .SCAN_OUT(pad143_sout), .SCAN_IN(pad142_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(ld_enlo_jtag), .HI_Z(hiz_jtag_east) ); bscan_cell pad178_jtag ( .PAD_OUT(\la_out_jtag[7] ), .PAD_ENB(pad178_en), .PAD_IN(\la_in_ah[7] ), .CORE_ENBZ(la_en_rz), .CORE_IN(\la_out_rh[7] ), .SCAN_OUT(pad178_sout), .SCAN_IN(pad177_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east ), .DIR_CNTL(la_en_jtag), .HI_Z(hiz_jtag_east) ); ipb_ph_in_5t_s pad10 ( .PADPIN(RS[1]), .Y(\rs_ah[1] ) ); bscan_cell pad6_jtag ( .PAD_OUT(\td_jtag_ah[0] ), .PAD_ENB(pad6_en), .PAD_IN(\td_jtag_ah[0] ), .CORE_ENBZ(1'b0), .CORE_IN(\td_ah[0] ), .SCAN_OUT(pad6_sout), .SCAN_IN(pad5_sout), .SHIFTDR(shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west ), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad71_jtag ( .PAD_OUT(\pci_ad_out_jtag[31] ), .PAD_ENB(pad71_en ), .PAD_IN(\pci_ad_in[31] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN( \pci_ad_out[31] ), .SCAN_OUT(pad71_sout), .SCAN_IN(pad_cntl_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pad_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad97_jtag ( .PAD_OUT(pci_stop_out_jtag), .PAD_ENB(pad97_en), .PAD_IN(pci_stop_in_l), .CORE_ENBZ(pci_trgt_en_l), .CORE_IN( pci_stop_out_l), .SCAN_OUT(pad97_sout), .SCAN_IN(pstop_cntl_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pstop_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_vd_all pad35_extra ( .VDDCORE(VDD) ); ipb_ph_in_5t_s pad37 ( .PADPIN(RS[4]), .Y(\rs_ah[4] ) ); ipb_ph_bi_08_5t_s pad101 ( .ENB(pad101_en), .IN0(pci_par_out_jtag), .Y( pci_par_in), .PADPIN(PPAR) ); ipb_ph_vs_all pad231 ( .GNDCORE(VSS) ); bscan_cell pad247_jtag ( .PAD_IN(\rc_ah[15] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad247_sout), .SCAN_IN(pad244_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_in_5t_s pad80 ( .PADPIN(PIDSEL), .Y(pci_idsel) ); bscan_cntl_cell pframe_cntl ( .SCAN_IN(pad92_sout), .SYS_LOGIC_CNTL( pci_frame_en_l), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .SHIFTDR(shift_dr_south), .RESET(rst_jtag_south), .SCAN_OUT( pframe_cntl_sout), .DIR_CNTL(pframe_en_jtag) ); ipb_ph_ou_04_5t pad126 ( .ENB(pad126_en), .IN0(pcix_ads_jtag), .PADPIN( PXAS) ); ipb_ph_ou_04_5t pad216 ( .ENB(pad216_en), .IN0(\td_jtag_ah[10] ), .PADPIN( TD[10]) ); ipb_ph_bi_04_5t_s pad191 ( .ENB(pad191_en), .IN0(\la_out_jtag[18] ), .Y( \la_in_ah[18] ), .PADPIN(LA[18]) ); bscan_cell pad251_jtag ( .PAD_IN(\ts_ah[15] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad251_sout), .SCAN_IN(pad250_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); ipb_ph_ou_04_5t pad42 ( .ENB(pad42_en), .IN0(\td_jtag_ah[4] ), .PADPIN(TD [4]) ); ipb_ph_in_5t_s pad65 ( .PADPIN(PRST), .Y(pci_rst) ); bscan_cell pad67_jtag ( .PAD_IN(pci_gnt_l), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad67_sout), .SCAN_IN(pad66_sout), .SHIFTDR( shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR(update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_south) ); bscan_cell pad197_jtag ( .PAD_IN(\rd_ah[8] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad197_sout), .SCAN_IN(pad196_sout), .SHIFTDR( shift_dr_north), .CLOCKDR(clk_dr_north), .UPDATEDR(update_dr_north), .MODE(mode_jtag_north), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_north) ); bscan_cell pad81_jtag ( .PAD_OUT(\pci_ad_out_jtag[23] ), .PAD_ENB(pad81_en ), .PAD_IN(\pci_ad_in[23] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN( \pci_ad_out[23] ), .SCAN_OUT(pad81_sout), .SCAN_IN(pad80_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pad_en_jtag), .HI_Z(hiz_jtag_south) ); ipb_ph_bi_04_5t_s pad174 ( .ENB(pad174_en), .IN0(\la_out_jtag[3] ), .Y( \la_in_ah[3] ), .PADPIN(LA[3]) ); bscan_cell pad155_jtag ( .PAD_IN(lms_ah), .CORE_ENBZ(1'b0), .CORE_IN(1'b0), .SCAN_OUT(pad155_sout), .SCAN_IN(pad154_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE(mode_jtag_east ), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_east) ); bscan_cell pad171_jtag ( .PAD_OUT(\la_out_jtag[0] ), .PAD_ENB(pad171_en), .PAD_IN(\la_in_ah[0] ), .CORE_ENBZ(la_en_rz), .CORE_IN(\la_out_rh[0] ), .SCAN_OUT(pad171_sout), .SCAN_IN(la_cntl_sout), .SHIFTDR(shift_dr_east ), .CLOCKDR(clk_dr_east), .UPDATEDR(update_dr_east), .MODE( mode_jtag_east), .DIR_CNTL(la_en_jtag), .HI_Z(hiz_jtag_east) ); ipb_ph_ou_04_5t pad244 ( .ENB(pad244_en), .IN0(\td_jtag_ah[14] ), .PADPIN( TD[14]) ); ipb_ph_bi_04_5t_s pad153 ( .ENB(pad153_en), .IN0(\ld_out_jtag[15] ), .Y( \ld_in_ah[15] ), .PADPIN(LD[15]) ); bscan_cell pad43_jtag ( .PAD_IN(\rc_ah[5] ), .CORE_ENBZ(1'b0), .CORE_IN( 1'b0), .SCAN_OUT(pad43_sout), .SCAN_IN(pad42_sout), .SHIFTDR( shift_dr_west), .CLOCKDR(clk_dr_west), .UPDATEDR(update_dr_west), .MODE(mode_jtag_west), .DIR_CNTL(1'b1), .HI_Z(hiz_jtag_west) ); bscan_cell pad78_jtag ( .PAD_OUT(\pci_ad_out_jtag[24] ), .PAD_ENB(pad78_en ), .PAD_IN(\pci_ad_in[24] ), .CORE_ENBZ(pci_ad_en_l), .CORE_IN( \pci_ad_out[24] ), .SCAN_OUT(pad78_sout), .SCAN_IN(pad77_sout), .SHIFTDR(shift_dr_south), .CLOCKDR(clk_dr_south), .UPDATEDR( update_dr_south), .MODE(mode_jtag_south), .DIR_CNTL(pad_en_jtag), .HI_Z(hiz_jtag_south) ); bscan_cell pad188_jtag ( .PAD_OUT(\la_out_jtag[15] ), .PAD_ENB(pad188_en), .PAD_IN(\la_in_ah[15] ), .CORE_ENBZ(la_en_rz), .CORE_IN( \la_out_rh[15] ), .SCAN_OUT(pad188_sout), .SCAN_IN(pad187_sout), .SHIFTDR(shift_dr_east), .CLOCKDR(clk_dr_east), .UPDATEDR( update_dr_east), .MODE(mode_jtag_east), .DIR_CNTL(la_en_jtag), .HI_Z( hiz_jtag_east) ); endmodule //----------------------------------------------------------------------- //end of ds31256_revB2_top_gat_no_core.v //----------------------------------------------------------------------- //----------------------------------------------------------------------- //beginning of ds31256_revB2_cell_lib.v //----------------------------------------------------------------------- // =================================================================== // $Id: ds31256_revB2_top_gat_bsdl.v_release.rca 1.1 Wed Jun 11 17:42:56 2003 dmurphy Experimental $ // =================================================================== // Copyright (c) 2003 Dallas Semiconductor // All Rights Reserved. // // THIS MATERIAL IS CONSIDERED CONFIDENTIAL AND PROPRIETARY BY // Dallas Semiconductor. UNAUTHORIZED ACCESS OR USE IS PROHIBITED. // =================================================================== // $RCSfile: ds31256_revB2_top_gat_bsdl.v_release.rca $ // $Author: dmurphy $ // =================================================================== // Revision History : // $Log: ds31256_revB2_top_gat_bsdl.v_release.rca $ // // Revision: 1.1 Wed Jun 11 17:42:56 2003 dmurphy // // DS31256 revB2 bsdl customer handoff item. this is identical // to revB1, but has a file name change. // // // =================================================================== //############################################################################# // // The file was manually generated. It is a collection of the models for all // the cells listed in $DS3134_BASE/bsdl/ds31256_revB2_lib_cell_list_gat.txt // which was generated by running the script $DS3134_BASE/bsdl/gen_netlist.scr. // // The purpose is to contain simulation models for all modules instantiated // in the core-less DS31256 module. These models are used to create a // stand-alone simulatable model of a core-less DS31256. // // Here is the list of models contained in this file: // // bscan_worst/dffacqs1lu // bscan_worst/dffqs2lu // bscan_worst/dln1d3lu // bscan_worst/hi1s1lu // bscan_worst/i1s1lu // bscan_worst/i1s2lu // bscan_worst/i1s3lu // bscan_worst/i1s7lu // bscan_worst/i1s9lu // bscan_worst/ib1s2lu // bscan_worst/ib1s3lu // bscan_worst/ib1s6lu // bscan_worst/mxi21s2lu // bscan_worst/nb1s6lu // bscan_worst/nor2s1lu // bscan_worst/nor2s2lu // bscan_worst/oai21s3lu // csm0_35_v2_1_1_worst/and2s1 // csm0_35_v2_1_1_worst/and2s3 // csm0_35_v2_1_1_worst/aoi211s3 // csm0_35_v2_1_1_worst/dffacqs1 // csm0_35_v2_1_1_worst/dffacqs2 // csm0_35_v2_1_1_worst/dffasqs1 // csm0_35_v2_1_1_worst/dffqs2 // csm0_35_v2_1_1_worst/dln094d2 // csm0_35_v2_1_1_worst/dln174d6 // csm0_35_v2_1_1_worst/hi1s1 // csm0_35_v2_1_1_worst/i1s1 // csm0_35_v2_1_1_worst/i1s10 // csm0_35_v2_1_1_worst/i1s11 // csm0_35_v2_1_1_worst/i1s3 // csm0_35_v2_1_1_worst/i1s4 // csm0_35_v2_1_1_worst/i1s5 // csm0_35_v2_1_1_worst/mx21s1 // csm0_35_v2_1_1_worst/mxi21s1 // csm0_35_v2_1_1_worst/mxi21s2 // csm0_35_v2_1_1_worst/nb1s1 // csm0_35_v2_1_1_worst/nnd2s1 // csm0_35_v2_1_1_worst/nnd2s2 // csm0_35_v2_1_1_worst/nnd3s1 // csm0_35_v2_1_1_worst/nnd3s2 // csm0_35_v2_1_1_worst/nor2s1 // csm0_35_v2_1_1_worst/nor3s1 // csm0_35_v2_1_1_worst/oai21s1 // csm0_35_v2_1_1_worst/oai21s3 // csm0_35_v2_1_1_worst/or2s1 // csm0_35_v2_1_1_worst/or2s2 // csm0_35_v2_1_1_worst/s2cd1s1 // csm0_35_v2_1_1_worst/xor2s1 // ipb_8mA_worst/ipb_ph_bi_04_5t_s // ipb_8mA_worst/ipb_ph_bi_04_5t_s_od // ipb_8mA_worst/ipb_ph_bi_04_5t_s_up // ipb_8mA_worst/ipb_ph_bi_08_5t_s // ipb_8mA_worst/ipb_ph_in_5t_s // ipb_8mA_worst/ipb_ph_ou_04_5t //############################################################################# //----------------------------------------------------------------------- // bscan_worst/dffacqs1lu //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module dffacqs1lu ( DIN, CLRB, CLK, OUT ); output OUT; input CLK; input CLRB; input DIN; reg notifier; not _i0 (_N1,CLRB); p_ffr _i1 (OUT,DIN,CLK,_N1,notifier); buf _wi0 (SHCHECKCLKCLRBLH,DIN); buf _wi1 (SHCHECKCLKDINLH,CLRB); specify // arc DIN --> OUT specparam input_cap_DIN_OUT = 1:1:1; // arc CLRB --> OUT specparam input_cap_CLRB_OUT = 1:1:1; specparam output_rise_transition_CLRB_OUT = 1:1:1; specparam output_fall_transition_CLRB_OUT = 1:1:1; specparam intrinsic_delay_rise_CLRB_OUT = 1:1:1; specparam intrinsic_delay_fall_CLRB_OUT = 1:1:1; (CLRB => OUT) = (intrinsic_delay_rise_CLRB_OUT, intrinsic_delay_fall_CLRB_OUT); specparam intrinsic_delay_rise_CLRB_OUT_s1 = 1:1:1; specparam intrinsic_delay_fall_CLRB_OUT_s1 = 1:1:1; if (DIN) (CLRB => OUT) = (intrinsic_delay_rise_CLRB_OUT_s1, intrinsic_delay_fall_CLRB_OUT_s1); // arc CLK --> OUT specparam input_cap_CLK_OUT = 1:1:1; specparam output_rise_transition_CLK_OUT = 1:1:1; specparam output_fall_transition_CLK_OUT = 1:1:1; specparam intrinsic_delay_rise_CLK_OUT = 1:1:1; specparam intrinsic_delay_fall_CLK_OUT = 1:1:1; (CLK => OUT) = (intrinsic_delay_rise_CLK_OUT, intrinsic_delay_fall_CLK_OUT); specparam intrinsic_delay_rise_CLK_OUT_s1 = 1:1:1; specparam intrinsic_delay_fall_CLK_OUT_s1 = 1:1:1; if (CLRB) (CLK => OUT) = (intrinsic_delay_rise_CLK_OUT_s1, intrinsic_delay_fall_CLK_OUT_s1); specparam setup_DIN_CLK = 1:1:1; specparam hold_DIN_CLK = 1:1:1; //$setuphold( posedge CLK, DIN, setup_DIN_CLK, hold_DIN_CLK, notifier ); specparam removal_CLRB_CLK = 1:1:1; specparam recovery_CLRB_CLK = 1:1:1; $recovery( posedge CLK, posedge CLRB, recovery_CLRB_CLK, notifier ); $hold( posedge CLK, CLRB, removal_CLRB_CLK, notifier ); //$width(posedge CLK, 1, 0, notifier); //$width(negedge CLK, 1, 0, notifier); //$width(negedge CLRB, 1, 0, notifier); endspecify endmodule // dffacqs1lu // `endcelldefine //----------------------------------------------------------------------- // bscan_worst/dffqs2lu //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module dffqs2lu ( DIN, CLK, OUT ); output OUT; input CLK; input DIN; reg notifier; p_ff _i0 (OUT, DIN, CLK, notifier); specify // arc DIN --> OUT specparam input_cap_DIN_OUT = 1:1:1; // arc CLK --> OUT specparam input_cap_CLK_OUT = 1:1:1; specparam output_rise_transition_CLK_OUT = 1:1:1; specparam output_fall_transition_CLK_OUT = 1:1:1; specparam intrinsic_delay_rise_CLK_OUT = 1:1:1; specparam intrinsic_delay_fall_CLK_OUT = 1:1:1; (CLK => OUT) = (intrinsic_delay_rise_CLK_OUT, intrinsic_delay_fall_CLK_OUT); specparam setup_DIN_CLK = 1:1:1; specparam hold_DIN_CLK = 1:1:1; //$setuphold( posedge CLK, DIN, setup_DIN_CLK, hold_DIN_CLK, notifier ); //$width(posedge CLK, 1, 0, notifier); //$width(negedge CLK, 1, 0, notifier); endspecify endmodule // dffqs2 // `endcelldefine //----------------------------------------------------------------------- // bscan_worst/dln1d3lu //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module dln1d3lu (OUT, IN); output OUT; input IN; buf _i0 (OUT,IN); // specify (IN => OUT) = (1, 1); // endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // bscan_worst/hi1s1lu //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module hi1s1lu (OUT, IN); output OUT; input IN; not _i0 (OUT,IN); // specify (IN => OUT) = (1, 1); // endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // bscan_worst/i1s1lu //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module i1s1lu (OUT, IN); output OUT; input IN; not _i0 (OUT,IN); // specify (IN => OUT) = (1, 1); // endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // bscan_worst/i1s2lu //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module i1s2lu (OUT, IN); output OUT; input IN; not _i0 (OUT,IN); // specify (IN => OUT) = (1, 1); // endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // bscan_worst/i1s3lu //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module i1s3lu (OUT, IN); output OUT; input IN; not _i0 (OUT,IN); // specify (IN => OUT) = (1, 1); // endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // bscan_worst/i1s7lu //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module i1s7lu (OUT, IN); output OUT; input IN; not _i0 (OUT,IN); // specify (IN => OUT) = (1, 1); // endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // bscan_worst/i1s9lu //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module i1s9lu (OUT, IN); output OUT; input IN; not _i0 (OUT,IN); // specify (IN => OUT) = (1, 1); // endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // bscan_worst/ib1s2lu //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module ib1s2lu (OUT, IN); output OUT; input IN; not _i0 (OUT,IN); // specify (IN => OUT) = (1, 1); // endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // bscan_worst/ib1s3lu //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module ib1s3lu(OUT, IN); output OUT; input IN; not _i0 (OUT,IN); // specify (IN => OUT) = (1, 1); // endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // bscan_worst/ib1s6lu //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module ib1s6lu (OUT, IN); output OUT; input IN; not _i0 (OUT,IN); // specify (IN => OUT) = (1, 1); // endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // bscan_worst/mxi21s2lu //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module mxi21s2lu (OUT, IN1, IN2, SIN); output OUT; input IN1; input IN2; input SIN; not _i0 (_N2,SIN); and _i1 (_N1,IN1,_N2); and _i2 (_N3,IN2,SIN); nor _i3 (OUT,_N1,_N3); // specify (IN1 => OUT) = (1, 1); // (IN2 => OUT) = (1, 1); // if(!IN1&IN2) (SIN => OUT) = (1, 1); // if(IN1&!IN2) (SIN => OUT) = (1, 1); // endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // bscan_worst/nb1s6lu //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module nb1s6lu (OUT, IN); output OUT; input IN; buf _i0 (OUT,IN); // specify (IN => OUT) = (1, 1); // endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // bscan_worst/nor2s1lu //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module nor2s1lu (OUT, IN1, IN2); output OUT; input IN1; input IN2; nor _i0 (OUT,IN1,IN2); // specify (IN1 => OUT) = (1, 1); // (IN2 => OUT) = (1, 1); // endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // bscan_worst/nor2s2lu //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module nor2s2lu (OUT, IN1, IN2); output OUT; input IN1; input IN2; nor _i0 (OUT,IN1,IN2); // specify (IN1 => OUT) = (1, 1); // (IN2 => OUT) = (1, 1); // endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // bscan_worst/oai21s3lu //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module oai21s3lu (OUT, IN1, IN2, IN3); output OUT; input IN1; input IN2; input IN3; or _i0 (_N1,IN1,IN2); nand _i1 (OUT,_N1,IN3); // specify (IN1 => OUT) = (1, 1); // (IN2 => OUT) = (1, 1); // (IN3 => OUT) = (1, 1); // endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/and2s1 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module and2s1 (OUT, IN1, IN2); output OUT; input IN1; input IN2; and _i0 (OUT,IN1,IN2); //specify (IN1 => OUT) = (1, 1); //(IN2 => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/and2s3 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module and2s3 (OUT, IN1, IN2); output OUT; input IN1; input IN2; and _i0 (OUT,IN1,IN2); //specify (IN1 => OUT) = (1, 1); //(IN2 => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/aoi211s3 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module aoi211s3 (OUT, IN1, IN2, IN3, IN4); output OUT; input IN1; input IN2; input IN3; input IN4; and _i0 (_N1,IN1,IN2); nor _i1 (OUT,IN4,_N1,IN3); //specify (IN1 => OUT) = (1, 1); //(IN2 => OUT) = (1, 1); //(IN3 => OUT) = (1, 1); //(IN4 => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/dffacqs1 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module dffacqs1 ( DIN, CLRB, CLK, OUT ); output OUT; input CLK; input CLRB; input DIN; reg notifier; not _i0 (_N1,CLRB); p_ffr _i1 (OUT,DIN,CLK,_N1,notifier); buf _wi0 (SHCHECKCLKCLRBLH,DIN); buf _wi1 (SHCHECKCLKDINLH,CLRB); specify // arc DIN --> OUT specparam input_cap_DIN_OUT = 1:1:1; // arc CLRB --> OUT specparam input_cap_CLRB_OUT = 1:1:1; specparam output_rise_transition_CLRB_OUT = 1:1:1; specparam output_fall_transition_CLRB_OUT = 1:1:1; specparam intrinsic_delay_rise_CLRB_OUT = 1:1:1; specparam intrinsic_delay_fall_CLRB_OUT = 1:1:1; (CLRB => OUT) = (intrinsic_delay_rise_CLRB_OUT, intrinsic_delay_fall_CLRB_OUT); specparam intrinsic_delay_rise_CLRB_OUT_s1 = 1:1:1; specparam intrinsic_delay_fall_CLRB_OUT_s1 = 1:1:1; if (DIN) (CLRB => OUT) = (intrinsic_delay_rise_CLRB_OUT_s1, intrinsic_delay_fall_CLRB_OUT_s1); // arc CLK --> OUT specparam input_cap_CLK_OUT = 1:1:1; specparam output_rise_transition_CLK_OUT = 1:1:1; specparam output_fall_transition_CLK_OUT = 1:1:1; specparam intrinsic_delay_rise_CLK_OUT = 1:1:1; specparam intrinsic_delay_fall_CLK_OUT = 1:1:1; (CLK => OUT) = (intrinsic_delay_rise_CLK_OUT, intrinsic_delay_fall_CLK_OUT); specparam intrinsic_delay_rise_CLK_OUT_s1 = 1:1:1; specparam intrinsic_delay_fall_CLK_OUT_s1 = 1:1:1; if (CLRB) (CLK => OUT) = (intrinsic_delay_rise_CLK_OUT_s1, intrinsic_delay_fall_CLK_OUT_s1); specparam setup_DIN_CLK = 1:1:1; specparam hold_DIN_CLK = 1:1:1; //$setuphold( posedge CLK, DIN, setup_DIN_CLK, hold_DIN_CLK, notifier ); specparam removal_CLRB_CLK = 1:1:1; specparam recovery_CLRB_CLK = 1:1:1; $recovery( posedge CLK, posedge CLRB, recovery_CLRB_CLK, notifier ); $hold( posedge CLK, CLRB, removal_CLRB_CLK, notifier ); //$width(posedge CLK, 1, 0, notifier); //$width(negedge CLK, 1, 0, notifier); //$width(negedge CLRB, 1, 0, notifier); endspecify endmodule // dffacqs1 // `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/dffacqs2 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module dffacqs2 ( DIN, CLRB, CLK, OUT ); output OUT; input CLK; input CLRB; input DIN; reg notifier; not _i0 (_N1,CLRB); p_ffr _i1 (OUT,DIN,CLK,_N1,notifier); buf _wi0 (SHCHECKCLKCLRBLH,DIN); buf _wi1 (SHCHECKCLKDINLH,CLRB); specify // arc DIN --> OUT specparam input_cap_DIN_OUT = 1:1:1; // arc CLRB --> OUT specparam input_cap_CLRB_OUT = 1:1:1; specparam output_rise_transition_CLRB_OUT = 1:1:1; specparam output_fall_transition_CLRB_OUT = 1:1:1; specparam intrinsic_delay_rise_CLRB_OUT = 1:1:1; specparam intrinsic_delay_fall_CLRB_OUT = 1:1:1; (CLRB => OUT) = (intrinsic_delay_rise_CLRB_OUT, intrinsic_delay_fall_CLRB_OUT); specparam intrinsic_delay_rise_CLRB_OUT_s1 = 1:1:1; specparam intrinsic_delay_fall_CLRB_OUT_s1 = 1:1:1; if (DIN) (CLRB => OUT) = (intrinsic_delay_rise_CLRB_OUT_s1, intrinsic_delay_fall_CLRB_OUT_s1); // arc CLK --> OUT specparam input_cap_CLK_OUT = 1:1:1; specparam output_rise_transition_CLK_OUT = 1:1:1; specparam output_fall_transition_CLK_OUT = 1:1:1; specparam intrinsic_delay_rise_CLK_OUT = 1:1:1; specparam intrinsic_delay_fall_CLK_OUT = 1:1:1; (CLK => OUT) = (intrinsic_delay_rise_CLK_OUT, intrinsic_delay_fall_CLK_OUT); specparam intrinsic_delay_rise_CLK_OUT_s1 = 1:1:1; specparam intrinsic_delay_fall_CLK_OUT_s1 = 1:1:1; if (CLRB) (CLK => OUT) = (intrinsic_delay_rise_CLK_OUT_s1, intrinsic_delay_fall_CLK_OUT_s1); specparam setup_DIN_CLK = 1:1:1; specparam hold_DIN_CLK = 1:1:1; //$setuphold( posedge CLK, DIN, setup_DIN_CLK, hold_DIN_CLK, notifier ); specparam removal_CLRB_CLK = 1:1:1; specparam recovery_CLRB_CLK = 1:1:1; $recovery( posedge CLK, posedge CLRB, recovery_CLRB_CLK, notifier ); $hold( posedge CLK, CLRB, removal_CLRB_CLK, notifier ); //$width(posedge CLK, 1, 0, notifier); //$width(negedge CLK, 1, 0, notifier); //$width(negedge CLRB, 1, 0, notifier); endspecify endmodule // dffacqs2 // `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/dffasqs1 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module dffasqs1 ( DIN, SETB, CLK, OUT ); output OUT; input CLK; input DIN; input SETB; reg notifier; not _i0 (_N1,SETB); p_ffs _i1 (OUT,DIN,CLK,_N1,notifier); buf _wi0 (SHCHECKCLKDINLH,SETB); not _wi1 (SHCHECKCLKSETBLH,DIN); specify // arc DIN --> OUT specparam input_cap_DIN_OUT = 1:1:1; // arc SETB --> OUT specparam input_cap_SETB_OUT = 1:1:1; specparam output_rise_transition_SETB_OUT = 1:1:1; specparam output_fall_transition_SETB_OUT = 1:1:1; specparam intrinsic_delay_rise_SETB_OUT = 1:1:1; specparam intrinsic_delay_fall_SETB_OUT = 1:1:1; (SETB => OUT) = (intrinsic_delay_rise_SETB_OUT, intrinsic_delay_fall_SETB_OUT); specparam intrinsic_delay_rise_SETB_OUT_s1 = 1:1:1; specparam intrinsic_delay_fall_SETB_OUT_s1 = 1:1:1; if (!DIN) (SETB => OUT) = (intrinsic_delay_rise_SETB_OUT_s1, intrinsic_delay_fall_SETB_OUT_s1); // arc CLK --> OUT specparam input_cap_CLK_OUT = 1:1:1; specparam output_rise_transition_CLK_OUT = 1:1:1; specparam output_fall_transition_CLK_OUT = 1:1:1; specparam intrinsic_delay_rise_CLK_OUT = 1:1:1; specparam intrinsic_delay_fall_CLK_OUT = 1:1:1; (CLK => OUT) = (intrinsic_delay_rise_CLK_OUT, intrinsic_delay_fall_CLK_OUT); specparam intrinsic_delay_rise_CLK_OUT_s1 = 1:1:1; specparam intrinsic_delay_fall_CLK_OUT_s1 = 1:1:1; if (SETB) (CLK => OUT) = (intrinsic_delay_rise_CLK_OUT_s1, intrinsic_delay_fall_CLK_OUT_s1); specparam setup_DIN_CLK = 1:1:1; specparam hold_DIN_CLK = 1:1:1; //$setuphold( posedge CLK, DIN, setup_DIN_CLK, hold_DIN_CLK, notifier ); specparam removal_SETB_CLK = 1:1:1; specparam recovery_SETB_CLK = 1:1:1; $recovery( posedge CLK, posedge SETB, recovery_SETB_CLK, notifier ); $hold( posedge CLK, SETB, removal_SETB_CLK, notifier ); //$width(posedge CLK, 1, 0, notifier); //$width(negedge CLK, 1, 0, notifier); //$width(negedge SETB, 1, 0, notifier); endspecify endmodule // dffasqs1 // `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/dffqs2 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module dffqs2 ( DIN, CLK, OUT ); output OUT; input CLK; input DIN; reg notifier; p_ff _i0 (OUT, DIN, CLK, notifier); specify // arc DIN --> OUT specparam input_cap_DIN_OUT = 1:1:1; // arc CLK --> OUT specparam input_cap_CLK_OUT = 1:1:1; specparam output_rise_transition_CLK_OUT = 1:1:1; specparam output_fall_transition_CLK_OUT = 1:1:1; specparam intrinsic_delay_rise_CLK_OUT = 1:1:1; specparam intrinsic_delay_fall_CLK_OUT = 1:1:1; (CLK => OUT) = (intrinsic_delay_rise_CLK_OUT, intrinsic_delay_fall_CLK_OUT); specparam setup_DIN_CLK = 1:1:1; specparam hold_DIN_CLK = 1:1:1; //$setuphold( posedge CLK, DIN, setup_DIN_CLK, hold_DIN_CLK, notifier ); //$width(posedge CLK, 1, 0, notifier); //$width(negedge CLK, 1, 0, notifier); endspecify endmodule // dffqs2 // `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_1_worst/dln094d2 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module dln094d2 (OUT, IN); output OUT; input IN; buf _i0 (OUT,IN); // specify (IN => OUT) = (1, 1); // endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_1_worst/dln174d6 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module dln174d6 (OUT, IN); output OUT; input IN; buf _i0 (OUT,IN); // specify (IN => OUT) = (1, 1); // endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/hi1s1 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module hi1s1 (OUT, IN); output OUT; input IN; not _i0 (OUT,IN); //specify (IN => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/i1s1 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module i1s1 (OUT, IN); output OUT; input IN; not _i0 (OUT,IN); //specify (IN => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/i1s10 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module i1s10 (OUT, IN); output OUT; input IN; not _i0 (OUT,IN); //specify (IN => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/i1s11 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module i1s11 (OUT, IN); output OUT; input IN; not _i0 (OUT,IN); //specify (IN => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/i1s3 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module i1s3 (OUT, IN); output OUT; input IN; not _i0 (OUT,IN); //specify (IN => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/i1s4 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module i1s4 (OUT, IN); output OUT; input IN; not _i0 (OUT,IN); //specify (IN => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/i1s5 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module i1s5 (OUT, IN); output OUT; input IN; not _i0 (OUT,IN); //specify (IN => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/mx21s1 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module mx21s1 (OUT, IN1, IN2, SIN); output OUT; input IN1; input IN2; input SIN; not _i0 (_N2,SIN); and _i1 (_N1,IN1,_N2); and _i2 (_N3,IN2,SIN); or _i3 (OUT,_N1,_N3); //specify (IN1 => OUT) = (1, 1); // (IN2 => OUT) = (1, 1); // if(!IN1&IN2) (SIN => OUT) = (1, 1); // if(IN1&!IN2) (SIN => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/mxi21s1 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module mxi21s1 (OUT, IN1, IN2, SIN); output OUT; input IN1; input IN2; input SIN; not _i0 (_N2,SIN); and _i1 (_N1,IN1,_N2); and _i2 (_N3,IN2,SIN); nor _i3 (OUT,_N1,_N3); //specify (IN1 => OUT) = (1, 1); // (IN2 => OUT) = (1, 1); // if(!IN1&IN2) (SIN => OUT) = (1, 1); // if(IN1&!IN2) (SIN => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/mxi21s2 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module mxi21s2 (OUT, IN1, IN2, SIN); output OUT; input IN1; input IN2; input SIN; not _i0 (_N2,SIN); and _i1 (_N1,IN1,_N2); and _i2 (_N3,IN2,SIN); nor _i3 (OUT,_N1,_N3); //specify (IN1 => OUT) = (1, 1); // (IN2 => OUT) = (1, 1); // if(!IN1&IN2) (SIN => OUT) = (1, 1); // if(IN1&!IN2) (SIN => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/nb1s1 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module nb1s1 (OUT, IN); output OUT; input IN; buf _i0 (OUT,IN); //specify (IN => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/nnd2s1 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module nnd2s1 (OUT, IN1, IN2); output OUT; input IN1; input IN2; nand _i0 (OUT,IN1,IN2); //specify (IN1 => OUT) = (1, 1); // (IN2 => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/nnd2s2 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module nnd2s2 (OUT, IN1, IN2); output OUT; input IN1; input IN2; nand _i0 (OUT,IN1,IN2); //specify (IN1 => OUT) = (1, 1); // (IN2 => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/nnd3s1 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module nnd3s1 (OUT, IN1, IN2, IN3); output OUT; input IN1; input IN2; input IN3; nand _i0 (OUT,IN3,IN1,IN2); //specify (IN1 => OUT) = (1, 1); // (IN2 => OUT) = (1, 1); // (IN3 => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/nnd3s2 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module nnd3s2 (OUT, IN1, IN2, IN3); output OUT; input IN1; input IN2; input IN3; nand _i0 (OUT,IN3,IN1,IN2); //specify (IN1 => OUT) = (1, 1); // (IN2 => OUT) = (1, 1); // (IN3 => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/nor2s1 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module nor2s1 (OUT, IN1, IN2); output OUT; input IN1; input IN2; nor _i0 (OUT,IN1,IN2); //specify (IN1 => OUT) = (1, 1); // (IN2 => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/nor3s1 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module nor3s1 (OUT, IN1, IN2, IN3); output OUT; input IN1; input IN2; input IN3; nor _i0 (OUT,IN3,IN1,IN2); //specify (IN1 => OUT) = (1, 1); // (IN2 => OUT) = (1, 1); // (IN3 => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/oai21s1 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module oai21s1 (OUT, IN1, IN2, IN3); output OUT; input IN1; input IN2; input IN3; or _i0 (_N1,IN1,IN2); nand _i1 (OUT,_N1,IN3); //specify (IN1 => OUT) = (1, 1); // (IN2 => OUT) = (1, 1); // (IN3 => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/oai21s3 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module oai21s3 (OUT, IN1, IN2, IN3); output OUT; input IN1; input IN2; input IN3; or _i0 (_N1,IN1,IN2); nand _i1 (OUT,_N1,IN3); //specify (IN1 => OUT) = (1, 1); // (IN2 => OUT) = (1, 1); // (IN3 => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/or2s1 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module or2s1 (OUT, IN1, IN2); output OUT; input IN1; input IN2; or _i0 (OUT,IN1,IN2); //specify (IN1 => OUT) = (1, 1); // (IN2 => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/or2s2 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module or2s2 (OUT, IN1, IN2); output OUT; input IN1; input IN2; or _i0 (OUT,IN1,IN2); //specify (IN1 => OUT) = (1, 1); // (IN2 => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/s2cd1s1 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module s2cd1s1 (OUT, OUTB, IN); output OUT; output OUTB; input IN; buf _i0 (OUT,IN); not _i1 (OUTB,IN); //specify (IN => OUT) = (1, 1); // (IN => OUTB) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // csm0_35_v2_1_worst/xor2s1 //----------------------------------------------------------------------- //`timescale 1ns / 1ps `celldefine module xor2s1 (OUT, IN1, IN2); output OUT; input IN1; input IN2; xor _i0 (OUT,IN1,IN2); //specify // if(!IN1) (IN2 => OUT) = (1, 1); // if(!IN2) (IN1 => OUT) = (1, 1); // if(IN1) (IN2 => OUT) = (1, 1); // if(IN2) (IN1 => OUT) = (1, 1); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // ipb_8mA_worst/ipb_ph_bi_04_5t_s //----------------------------------------------------------------------- module ipb_ph_bi_04_5t_s (IN0,Y,ENB,PADPIN); output Y; input IN0,ENB; inout PADPIN; bufif0 #1 (PADPIN,IN0,ENB); buf #1 (Y,PADPIN); endmodule //----------------------------------------------------------------------- // ipb_8mA_worst/ipb_ph_bi_04_5t_s_od // commented out. see below. DM 10/25/02. //----------------------------------------------------------------------- //module ipb_ph_bi_04_5t_s_od (IN0,Y,ENB,PADPIN); // //output Y; //input IN0,ENB; //inout PADPIN; // ////bufif0 #1 (PADPIN,IN0,ENB|IN0); //bufif0 #1 (PADPIN,IN0,ENB); //buf #1 (Y,PADPIN); // //endmodule // //----------------------------------------------------------------------- // open_drain_models.v // used to replace incorrect model in verilog library file. //----------------------------------------------------------------------- //----------------------------------------------------------------------- // cs.35u4m1pS_cs35_75u_v1/ipb_ph_bi_04_5t_s_od //----------------------------------------------------------------------- module ipb_ph_bi_04_5t_s_od (ENB, IN0, PADPIN, Y); input ENB; input IN0; inout PADPIN; output Y; wire n2; cda_tristate inst1 (.enbar(ENB || IN0), .in(IN0), .out(PADPIN)); cda_inv inst2 (.in(PADPIN), .out(n2)); cda_inv inst3 (.in(n2), .out(Y)); endmodule //----------------------------------------------------------------------- // cda_inv -- primitive required by Cascade I/O cells (ipb_ph_*) //----------------------------------------------------------------------- `celldefine module cda_inv (in, out); input in; output out; not (out, in); //specify // (in => out) = (0,0); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // cda_tristate -- primitive required by Cascade I/O cells (ipb_ph_*) //----------------------------------------------------------------------- `celldefine module cda_tristate(enbar, in, out); input in, enbar; output out; // trireg (large) out; supply1 vdd; bufif0(outi, in, enbar); nmos (out, outi, vdd); //specify // (in => out) = (0,0); // (enbar => out) = (0,0); //endspecify endmodule `endcelldefine //----------------------------------------------------------------------- // end of open_drain_models.v //----------------------------------------------------------------------- //----------------------------------------------------------------------- // ipb_8mA_worst/ipb_ph_bi_04_5t_s_up //----------------------------------------------------------------------- module ipb_ph_bi_04_5t_s_up (IN0,Y,ENB,PADPIN); output Y; input IN0,ENB; inout PADPIN; bufif0 #1 (PADPIN,IN0,ENB); buf #1 (Y,PADPIN); endmodule //----------------------------------------------------------------------- // ipb_8mA_worst/ipb_ph_bi_08_5t_s //----------------------------------------------------------------------- module ipb_ph_bi_08_5t_s (IN0,Y,ENB,PADPIN); output Y; input IN0,ENB; inout PADPIN; bufif0 #1 (PADPIN,IN0,ENB); buf #1 (Y,PADPIN); endmodule //----------------------------------------------------------------------- // ipb_8mA_worst/ipb_ph_in_5t_s //----------------------------------------------------------------------- module ipb_ph_in_5t_s (Y,PADPIN); output Y; input PADPIN; buf #1 (Y,PADPIN); endmodule //----------------------------------------------------------------------- // ipb_8mA_worst/ipb_ph_ou_04_5t //----------------------------------------------------------------------- module ipb_ph_ou_04_5t (IN0,ENB,PADPIN); output PADPIN; input IN0,ENB; bufif0 #1 (PADPIN,IN0,ENB); endmodule //----------------------------------------------------------------------- // p_ff -- verilog primitive required by above modules //----------------------------------------------------------------------- primitive p_ff (Q, D, CP,notifier); output Q; reg Q; input D, CP,notifier; table // D CP No : Qt : Qt+1 1 (01) ? : ? : 1; // clocked data 0 (01) ? : ? : 0; 1 (x1) ? : 1 : 1; // reducing pessimism 0 (x1) ? : 0 : 0; 1 (0x) ? : 1 : 1; 0 (0x) ? : 0 : 0; ? (1x) ? : ? : -; // no change on falling edge ? (?0) ? : ? : -; * ? ? : ? : -; // ignore edges on data ? ? * : ? : x; endtable endprimitive //----------------------------------------------------------------------- // p_ffr -- verilog primitive required by above modules //----------------------------------------------------------------------- primitive p_ffr (Q, D, CP, R, notifier); output Q; reg Q; input D, CP, R, notifier; table // D CP R No : Qt : Qt+1 1 (01) 0 ? : ? : 1; // clocked data 0 (01) 0 ? : ? : 0; 0 (01) x ? : ? : 0; // pessimism 0 ? x ? : 0 : 0; // pessimism 1 0 x ? : 0 : 0; // pessimism 1 x (?x) ? : 0 : 0; // pessimism 1 1 (?x) ? : 0 : 0; // pessimism x 0 x ? : 0 : 0; // pessimism x x (?x) ? : 0 : 0; // pessimism x 1 (?x) ? : 0 : 0; // pessimism 1 (x1) 0 ? : 1 : 1; // reducing pessimism 0 (x1) 0 ? : 0 : 0; 1 (0x) 0 ? : 1 : 1; 0 (0x) 0 ? : 0 : 0; ? ? 1 ? : ? : 0; // asynchronous clear ? (?0) ? ? : ? : -; // ignore falling clock ? (1x) ? ? : ? : -; // ignore falling clock * ? ? ? : ? : -; // ignore the edges on data ? ? (?0) ? : ? : -; // ignore the edges on clear ? ? ? * : ? : x; endtable endprimitive //----------------------------------------------------------------------- // p_ffs -- verilog primitive required by above modules //----------------------------------------------------------------------- primitive p_ffs (Q, D, CP, S, notifier); output Q; reg Q; input D, CP, S, notifier; table // D CP S No : Qt : Qt+1 1 (01) 0 ? : ? : 1; // clocked data 0 (01) 0 ? : ? : 0; 1 (01) x ? : ? : 1; // reducing pessimism 1 ? x ? : 1 : 1; // pessimism 0 0 x ? : 1 : 1; // pessimism 0 x (?x) ? : 1 : 1; // pessimism 0 1 (?x) ? : 1 : 1; // pessimism x 0 x ? : 1 : 1; // pessimism x x (?x) ? : 1 : 1; // pessimism x 1 (?x) ? : 1 : 1; // pessimism 1 (x1) 0 ? : 1 : 1; // reducing pessimism 0 (x1) 0 ? : 0 : 0; 1 (0x) 0 ? : 1 : 1; 0 (0x) 0 ? : 0 : 0; ? ? 1 ? : ? : 1; // asynchronous clear ? (?0) ? ? : ? : -; // ignore falling clock ? (1x) ? ? : ? : -; // ignore falling clock * ? ? ? : ? : -; // ignore the data edges ? ? (?0) ? : ? : -; // ignore the edges on set ? ? ? * : ? : x; endtable endprimitive //----------------------------------------------------------------------- //end of ds31256_revB2_cell_lib.v //----------------------------------------------------------------------- //----------------------------------------------------------------------- //end of ds31256_revB2_top_gat_bsdl.v //-----------------------------------------------------------------------