-- *********************************************************************** -- BSDL file for design ds26519_wrapper -- Created by Synopsys Version 2000.11 (Nov 27, 2000) -- Designer: arichter -- Company: Dallas Semiconductor/Maxim -- Date: Thu Nov 30 18:10:04 2006 -- *********************************************************************** entity ds26519_wrapper is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "CSBGA_484"); -- This section declares all the ports in the design. port ( DIGIOEN : in bit; JTCLK : in bit; JTDI : in bit; JTMS : in bit; JTRST_N : in bit; BPCLK1 : inout bit; BPCLK2 : inout bit; BTS : inout bit; CLKO : inout bit; CSB : inout bit; INTB : inout bit; MCLK : inout bit; RDB : inout bit; REFCLKIO : inout bit; RESETB : inout bit; RESREF : inout bit; SCAN_EN : inout bit; SCAN_MODE : inout bit; SPI_SEL : inout bit; TST_RA1 : inout bit; TST_RB1 : inout bit; TST_RC1 : inout bit; TST_TA1 : inout bit; TST_TB1 : inout bit; TST_TC1 : inout bit; TX_ENABLE : inout bit; WRB : inout bit; A : inout bit_vector (0 to 13); D : inout bit_vector (0 to 7); GPIO : inout bit_vector (1 to 16); RCHBLK : inout bit_vector (1 to 16); RCLK : inout bit_vector (1 to 16); RMSYNC : inout bit_vector (1 to 16); RRING : inout bit_vector (1 to 16); RSER : inout bit_vector (1 to 16); RSIG : inout bit_vector (1 to 16); RSYNC : inout bit_vector (1 to 16); RSYSCLK : inout bit_vector (1 to 16); RTIP : inout bit_vector (1 to 16); RTIPE : inout bit_vector (1 to 16); TCHBLK : inout bit_vector (1 to 16); TCLK : inout bit_vector (1 to 16); TRING : inout bit_vector (1 to 32); TSER : inout bit_vector (1 to 16); TSIG : inout bit_vector (1 to 16); TSYNC : inout bit_vector (1 to 16); TSYSCLK : inout bit_vector (1 to 16); TTIP : inout bit_vector (1 to 32); VDD18 : inout bit_vector (1 to 6); VDD33 : inout bit_vector (1 to 42); VSS : inout bit_vector (1 to 50); JTDO : out bit ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of ds26519_wrapper: entity is "STD_1149_1_1993"; attribute PIN_MAP of ds26519_wrapper: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information -- is extracted from the port-to-pin map file that was read in using -- the "read_pin_map" command. constant CSBGA_484: PIN_MAP_STRING := "DIGIOEN : A14," & "JTCLK : E3," & "JTDI : G5," & "JTMS : G4," & "JTRST_N : F4," & "BPCLK1 : H8," & "BPCLK2 : R17," & "BTS : U15," & "CLKO : C3," & "CSB : W8," & "INTB : U9," & "MCLK : F11," & "RDB : Y8," & "REFCLKIO : A18," & "RESETB : T16," & "RESREF : E5," & "SCAN_EN : N6," & "SCAN_MODE : V18," & "SPI_SEL : F5," & "TST_RA1 : K2," & "TST_RB1 : P6," & "TST_RC1 : L2," & "TST_TA1 : T6," & "TST_TB1 : K1," & "TST_TC1 : R6," & "TX_ENABLE : U16," & "WRB : R13," & "A : (C16, F12, A20, G11, H9, A21, F13, A22, H10, B19, H11" & ", D15, G13, B20)," & "D : (Y9, U8, AA6, T14, AB5, R14, AA5, P14)," & "GPIO : (P22, J17, N21, B13, F10, W19, P19, N18, T22, K17, " & "M19, K16, R21, J15, R22, J16)," & "RCHBLK : (F3, G8, H5, Y7, AA8, AA11, E18, U20, G7, L15, B2, W4" & ", M6, U17, H14, R16)," & "RCLK : (J9, H7, J8, H6, T15, U19, V20, W20, D3, C2, H3, G3, " & "T17, R15, T18, N15)," & "RMSYNC : (C13, C15, V7, T9, T13, U13, D16, W21, T21, V22, V6, " & "H4, G1, K4, F15, N17)," & "RRING : (A4, R2, V2, Y1, AB20, H22, F21, D22, AB12, AA15, " & "AA18, N22, A12, B9, A6, N2)," & "RSER : (D12, E12, J5, AA4, Y10, AA10, B18, T20, L17, L16, B1" & ", K7, J4, P7, H13, M16)," & "RSIG : (D4, B16, J7, R10, U10, V11, H17, V19, F6, P20, D2, " & "Y4, J3, K3, J14, P15)," & "RSYNC : (F9, E13, T7, W3, W9, AB9, A19, Y19, N19, P17, V5, L7" & ", L6, L5, E15, R18)," & "RSYSCLK : (U18, G9, J6, W7, AB7, AB10, C19, AA22, G6, P18, F2, " & "AB2, P8, R7, G15, T19)," & "RTIP : (B4, T2, U1, Y2, AA20, J21, G21, C21, AB13, AB15, " & "AB17, M22, A11, A9, B6, N1)," & "RTIPE : (A3, R1, V1, AA1, AB21, J22, F22, C22, AA13, AA16, " & "AB18, L22, A13, B8, A7, M1)," & "TCHBLK : (A15, A17, N9, V8, V9, W10, E14, H12, N20, W22, Y5, " & "K6, D1, G2, Y22, F16)," & "TCLK : (F7, G10, R8, AB4, AB6, AB8, B21, D18, K14, P16, W5, " & "M18, N8, N7, P21, D17)," & "TRING : (D6, E6, P4, P5, T4, T5, EU4, U5, W17, V17, J19, J18" & ", H19, H18, E20, E19, Y11, Y12, W14, V14, W15, V15, M20, L20, C12, " & "C11, D9, E9, D8, E8, L3, M3)," & "TSER : (B15, D14, T8, R12, T10, U11, C17, E17, U21, R20, W6" & ", C1, E1, H1, H15, F17)," & "TSIG : (B14, C14, P9, R11, T12, U12, B17, F14, U22, V21, U6" & ", A1, F1, H2, G14, G17)," & "TSYNC : (F8, D13, R9, AB3, AA7, AA9, D20, H16, K15, N16, Y6, " & "M8, M7, K5, D19, G16)," & "TSYSCLK : (W11, A16, K8, U7, V10, U14, C18, Y21, L4, R19, E2, " & "AA3, J1, J2, E16, M17)," & "TTIP : (C5, D5, N4, N5, R4, R5, V3, V4, Y18, W18, K19, K18, " & "G19, G18, F19, F18, W12, V12, W13, V13, W16, V16, L19, L18, D11, " & "E11, D10, E10, D7, E7, M4, M5)," & "VDD18 : (L8, M15, G12, T11, M9, L14)," & "VDD33 : (K9, N14, J11, J10, J12, P13, P10, J13, P11, P12, C4" & ", T1, T3, AA2, AA21, H21, E21, C20, AB11, Y15, AA19, K21, B11, A8, " & "B7, L1, C6, P3, U2, U3, Y17, K22, F20, E22, AB14, AB16, AA17, M21, " & "B10, C9, B5, P1)," & "VSS : (L12, M12, M13, M11, L13, M10, L10, L11, K13, K12, " & "K11, N11, N10, K10, N12, N13, L9, M14, B3, R3, W1, Y3, Y20, G22, " & "H20, B22, AA12, Y14, Y16, L21, B12, C8, A5, M2, A2, N3, W2, AB1, " & "AB22, J20, G20, D21, AA14, Y13, AB19, K20, A10, C10, C7, P2)," & "JTDO : E4"; -- This section specifies the TAP ports. -- For the TAP TCK port, the parameters in the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of JTCLK : signal is (10.0e6, BOTH); attribute TAP_SCAN_IN of JTDI : signal is true; attribute TAP_SCAN_MODE of JTMS : signal is true; attribute TAP_SCAN_OUT of JTDO : signal is true; attribute TAP_SCAN_RESET of JTRST_N: signal is true; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of ds26519_wrapper: entity is 3; -- Specifies the boundary-scan instructions implemented in the -- design and their opcodes. attribute INSTRUCTION_OPCODE of ds26519_wrapper: entity is "BYPASS (111)," & "EXTEST (000)," & "SAMPLE (010)," & "USER1 (100)," & "IDCODE (001)"; -- Specifies the bit pattern that is loaded into the instruction -- register when the TAP controller passes through the Capture-IR -- state. The standard mandates that the two LSBs must be "01". -- The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of ds26519_wrapper: entity is "001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID -- register during the IDCODE instruction when the TAP controller -- passes through the Capture-DR state. attribute IDCODE_REGISTER of ds26519_wrapper: entity is "0000" & -- 4-bit version number "0000000010001011" & -- 16-bit part number "00010100001" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 -- This section specifies the test data register placed between TDI -- and TDO for each implemented instruction. attribute REGISTER_ACCESS of ds26519_wrapper: entity is "BYPASS (BYPASS, USER1)," & "BOUNDARY (EXTEST, SAMPLE)," & "DEVICE_ID (IDCODE)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of ds26519_wrapper: entity is 522; -- The following list specifies the characteristics of each cell -- in the boundary scan register from TDI to TDO. -- The following is a description of the label fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not -- have a port name. -- function: Is the function of the cell as defined by the -- standard. Is one of input, output2, output3, -- bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be -- loaded with for safe operation when the software -- might otherwise choose a random value. -- ccell : The control cell number. Specifies the control -- cell that drives the output enable for this port. -- disval : Specifies the value that is loaded into the -- control cell to disable the output enable for -- the corresponding port. -- rslt : Resulting state. Shows the state of the driver -- when it is disabled. attribute BOUNDARY_REGISTER of ds26519_wrapper: entity is -- -- num cell port function safe [ccell disval rslt] -- "521 (BC_1, *, controlr, 0), " & "520 (BC_0, CLKO, bidir, X, 521, 0, Z), " & "519 (BC_1, *, controlr, 0), " & "518 (BC_0, SPI_SEL, bidir, X, 519, 0, PULL0)," & "517 (BC_1, *, controlr, 0), " & "516 (BC_0, RSYSCLK(9), bidir, X, 517, 0, Z), " & "515 (BC_1, *, controlr, 0), " & "514 (BC_0, RSIG(1), bidir, X, 515, 0, Z), " & "513 (BC_1, *, controlr, 0), " & "512 (BC_0, RSIG(9), bidir, X, 513, 0, Z), " & "511 (BC_1, *, controlr, 0), " & "510 (BC_0, RCHBLK(1), bidir, X, 511, 0, Z), " & "509 (BC_1, *, controlr, 0), " & "508 (BC_0, RCHBLK(9), bidir, X, 509, 0, Z), " & "507 (BC_1, *, controlr, 0), " & "506 (BC_0, RCLK(1), bidir, X, 507, 0, Z), " & "505 (BC_1, *, controlr, 0), " & "504 (BC_0, RCLK(9), bidir, X, 505, 0, Z), " & "503 (BC_1, *, controlr, 0), " & "502 (BC_0, RCLK(2), bidir, X, 503, 0, Z), " & "501 (BC_1, *, controlr, 0), " & "500 (BC_0, RCLK(10), bidir, X, 501, 0, Z), " & "499 (BC_1, *, controlr, 0), " & "498 (BC_0, RCLK(3), bidir, X, 499, 0, Z), " & "497 (BC_1, *, controlr, 0), " & "496 (BC_0, RCLK(11), bidir, X, 497, 0, Z), " & "495 (BC_1, *, controlr, 0), " & "494 (BC_0, RCLK(4), bidir, X, 495, 0, Z), " & "493 (BC_1, *, controlr, 0), " & "492 (BC_0, RCLK(12), bidir, X, 493, 0, Z), " & "491 (BC_1, *, controlr, 0), " & "490 (BC_0, RCHBLK(3), bidir, X, 491, 0, Z), " & "489 (BC_1, *, controlr, 0), " & "488 (BC_0, RCHBLK(11), bidir, X, 489, 0, Z), " & "487 (BC_1, *, controlr, 0), " & "486 (BC_0, RSIG(3), bidir, X, 487, 0, Z), " & "485 (BC_1, *, controlr, 0), " & "484 (BC_0, RSIG(11), bidir, X, 485, 0, Z), " & "483 (BC_1, *, controlr, 0), " & "482 (BC_0, TSYSCLK(3), bidir, X, 483, 0, PULL0)," & "481 (BC_1, *, controlr, 0), " & "480 (BC_0, TSYSCLK(11), bidir, X, 481, 0, Z), " & "479 (BC_1, *, controlr, 0), " & "478 (BC_0, RSYSCLK(3), bidir, X, 479, 0, PULL0)," & "477 (BC_1, *, controlr, 0), " & "476 (BC_0, RSYSCLK(11), bidir, X, 477, 0, Z), " & "475 (BC_1, *, controlr, 0), " & "474 (BC_0, RSER(3), bidir, X, 475, 0, Z), " & "473 (BC_1, *, controlr, 0), " & "472 (BC_0, RSER(11), bidir, X, 473, 0, Z), " & "471 (BC_1, *, controlr, 0), " & "470 (BC_0, RSER(12), bidir, X, 471, 0, Z), " & "469 (BC_1, *, controlr, 0), " & "468 (BC_0, RMSYNC(12), bidir, X, 469, 0, Z), " & "467 (BC_1, *, controlr, 0), " & "466 (BC_0, RSYNC(12), bidir, X, 467, 0, Z), " & "465 (BC_1, *, controlr, 0), " & "464 (BC_0, TSIG(12), bidir, X, 465, 0, Z), " & "463 (BC_1, *, controlr, 0), " & "462 (BC_0, TSYNC(12), bidir, X, 463, 0, Z), " & "461 (BC_1, *, controlr, 0), " & "460 (BC_0, TSER(12), bidir, X, 461, 0, Z), " & "459 (BC_1, *, controlr, 0), " & "458 (BC_0, TCHBLK(12), bidir, X, 459, 0, Z), " & "457 (BC_1, *, controlr, 0), " & "456 (BC_0, TCHBLK(13), bidir, X, 457, 0, Z), " & "455 (BC_1, *, controlr, 0), " & "454 (BC_0, TCLK(13), bidir, X, 455, 0, Z), " & "453 (BC_1, *, controlr, 0), " & "452 (BC_0, TSER(13), bidir, X, 453, 0, Z), " & "451 (BC_1, *, controlr, 0), " & "450 (BC_0, TSYNC(13), bidir, X, 451, 0, Z), " & "449 (BC_1, *, controlr, 0), " & "448 (BC_0, TSIG(13), bidir, X, 449, 0, Z), " & "447 (BC_1, *, controlr, 0), " & "446 (BC_0, RSYNC(13), bidir, X, 447, 0, Z), " & "445 (BC_1, *, controlr, 0), " & "444 (BC_0, RMSYNC(13), bidir, X, 445, 0, Z), " & "443 (BC_1, *, controlr, 0), " & "442 (BC_0, RSER(13), bidir, X, 443, 0, Z), " & "441 (BC_1, *, controlr, 0), " & "440 (BC_0, TSYSCLK(13), bidir, X, 441, 0, Z), " & "439 (BC_1, *, controlr, 0), " & "438 (BC_0, RSYSCLK(13), bidir, X, 439, 0, Z), " & "437 (BC_1, *, controlr, 0), " & "436 (BC_0, RSIG(13), bidir, X, 437, 0, Z), " & "435 (BC_1, *, controlr, 0), " & "434 (BC_0, RCHBLK(13), bidir, X, 435, 0, Z), " & "433 (BC_1, *, controlr, 0), " & "432 (BC_0, TCHBLK(14), bidir, X, 433, 0, Z), " & "431 (BC_1, *, controlr, 0), " & "430 (BC_0, TCLK(14), bidir, X, 431, 0, Z), " & "429 (BC_1, *, controlr, 0), " & "428 (BC_0, TSER(14), bidir, X, 429, 0, Z), " & "427 (BC_1, *, controlr, 0), " & "426 (BC_0, TSYNC(14), bidir, X, 427, 0, Z), " & "425 (BC_1, *, controlr, 0), " & "424 (BC_0, TSIG(14), bidir, X, 425, 0, Z), " & "423 (BC_1, *, controlr, 0), " & "422 (BC_0, RSYNC(14), bidir, X, 423, 0, Z), " & "421 (BC_1, *, controlr, 0), " & "420 (BC_0, RMSYNC(14), bidir, X, 421, 0, Z), " & "419 (BC_1, *, controlr, 0), " & "418 (BC_0, RSER(14), bidir, X, 419, 0, Z), " & "417 (BC_1, *, controlr, 0), " & "416 (BC_0, TSYSCLK(14), bidir, X, 417, 0, Z), " & "415 (BC_1, *, controlr, 0), " & "414 (BC_0, RSYSCLK(14), bidir, X, 415, 0, Z), " & "413 (BC_1, *, controlr, 0), " & "412 (BC_0, RSIG(14), bidir, X, 413, 0, Z), " & "411 (BC_1, *, controlr, 0), " & "410 (BC_0, SCAN_EN, bidir, X, 411, 0, Z), " & "409 (BC_1, *, controlr, 0), " & "408 (BC_0, TSYSCLK(9), bidir, X, 409, 0, Z), " & "407 (BC_1, *, controlr, 0), " & "406 (BC_0, TCLK(3), bidir, X, 407, 0, Z), " & "405 (BC_1, *, controlr, 0), " & "404 (BC_0, RMSYNC(11), bidir, X, 405, 0, Z), " & "403 (BC_1, *, controlr, 0), " & "402 (BC_0, RSYNC(3), bidir, X, 403, 0, Z), " & "401 (BC_1, *, controlr, 0), " & "400 (BC_0, RSYNC(11), bidir, X, 401, 0, Z), " & "399 (BC_1, *, controlr, 0), " & "398 (BC_0, TSIG(3), bidir, X, 399, 0, Z), " & "397 (BC_1, *, controlr, 0), " & "396 (BC_0, TSIG(11), bidir, X, 397, 0, Z), " & "395 (BC_1, *, controlr, 0), " & "394 (BC_0, TSYNC(3), bidir, X, 395, 0, Z), " & "393 (BC_1, *, controlr, 0), " & "392 (BC_0, TSYNC(11), bidir, X, 393, 0, Z), " & "391 (BC_1, *, controlr, 0), " & "390 (BC_0, TSER(3), bidir, X, 391, 0, Z), " & "389 (BC_1, *, controlr, 0), " & "388 (BC_0, TSER(11), bidir, X, 389, 0, Z), " & "387 (BC_1, *, controlr, 0), " & "386 (BC_0, RMSYNC(3), bidir, X, 387, 0, Z), " & "385 (BC_1, *, controlr, 0), " & "384 (BC_0, TCLK(11), bidir, X, 385, 0, Z), " & "383 (BC_1, *, controlr, 0), " & "382 (BC_0, TCHBLK(3), bidir, X, 383, 0, Z), " & "381 (BC_1, *, controlr, 0), " & "380 (BC_0, TCHBLK(11), bidir, X, 381, 0, Z), " & "379 (BC_1, *, controlr, 0), " & "378 (BC_0, RCHBLK(4), bidir, X, 379, 0, Z), " & "377 (BC_1, *, controlr, 0), " & "376 (BC_0, RCHBLK(12), bidir, X, 377, 0, Z), " & "375 (BC_1, *, controlr, 0), " & "374 (BC_0, RSIG(4), bidir, X, 375, 0, Z), " & "373 (BC_1, *, controlr, 0), " & "372 (BC_0, RSIG(12), bidir, X, 373, 0, Z), " & "371 (BC_1, *, controlr, 0), " & "370 (BC_0, RSYSCLK(4), bidir, X, 371, 0, PULL0)," & "369 (BC_1, *, controlr, 0), " & "368 (BC_0, RSYSCLK(12), bidir, X, 369, 0, Z), " & "367 (BC_1, *, controlr, 0), " & "366 (BC_0, TSYSCLK(4), bidir, X, 367, 0, PULL0)," & "365 (BC_1, *, controlr, 0), " & "364 (BC_0, TSYSCLK(12), bidir, X, 365, 0, Z), " & "363 (BC_1, *, controlr, 0), " & "362 (BC_0, RSER(4), bidir, X, 363, 0, Z), " & "361 (BC_1, *, controlr, 0), " & "360 (BC_0, RMSYNC(4), bidir, X, 361, 0, Z), " & "359 (BC_1, *, controlr, 0), " & "358 (BC_0, RSYNC(4), bidir, X, 359, 0, Z), " & "357 (BC_1, *, controlr, 0), " & "356 (BC_0, TSIG(4), bidir, X, 357, 0, Z), " & "355 (BC_1, *, controlr, 0), " & "354 (BC_0, TSYNC(4), bidir, X, 355, 0, Z), " & "353 (BC_1, *, controlr, 0), " & "352 (BC_0, TSER(4), bidir, X, 353, 0, Z), " & "351 (BC_1, *, controlr, 0), " & "350 (BC_0, TCLK(4), bidir, X, 351, 0, Z), " & "349 (BC_1, *, controlr, 0), " & "348 (BC_0, TCHBLK(4), bidir, X, 349, 0, Z), " & "347 (BC_1, *, controlr, 0), " & "346 (BC_0, CSB, bidir, X, 347, 0, Z), " & "345 (BC_1, *, controlr, 0), " & "344 (BC_0, WRB, bidir, X, 345, 0, Z), " & "343 (BC_1, *, controlr, 0), " & "342 (BC_0, RDB, bidir, X, 343, 0, Z), " & "341 (BC_1, *, controlr, 0), " & "340 (BC_0, D(0), bidir, X, 341, 0, Z), " & "339 (BC_1, *, controlr, 0), " & "338 (BC_0, D(1), bidir, X, 339, 0, Z), " & "337 (BC_1, *, controlr, 0), " & "336 (BC_0, D(2), bidir, X, 337, 0, Z), " & "335 (BC_1, *, controlr, 0), " & "334 (BC_0, D(3), bidir, X, 335, 0, Z), " & "333 (BC_1, *, controlr, 0), " & "332 (BC_0, D(4), bidir, X, 333, 0, Z), " & "331 (BC_1, *, controlr, 0), " & "330 (BC_0, D(5), bidir, X, 331, 0, Z), " & "329 (BC_1, *, controlr, 0), " & "328 (BC_0, D(6), bidir, X, 329, 0, Z), " & "327 (BC_1, *, controlr, 0), " & "326 (BC_0, D(7), bidir, X, 327, 0, Z), " & "325 (BC_1, *, controlr, 0), " & "324 (BC_0, INTB, bidir, X, 325, 0, Z), " & "323 (BC_1, *, controlr, 0), " & "322 (BC_0, TCHBLK(5), bidir, X, 323, 0, Z), " & "321 (BC_1, *, controlr, 0), " & "320 (BC_0, TCLK(5), bidir, X, 321, 0, Z), " & "319 (BC_1, *, controlr, 0), " & "318 (BC_0, TSER(5), bidir, X, 319, 0, Z), " & "317 (BC_1, *, controlr, 0), " & "316 (BC_0, TSYNC(5), bidir, X, 317, 0, Z), " & "315 (BC_1, *, controlr, 0), " & "314 (BC_0, TSIG(5), bidir, X, 315, 0, Z), " & "313 (BC_1, *, controlr, 0), " & "312 (BC_0, RSYNC(5), bidir, X, 313, 0, Z), " & "311 (BC_1, *, controlr, 0), " & "310 (BC_0, RMSYNC(5), bidir, X, 311, 0, Z), " & "309 (BC_1, *, controlr, 0), " & "308 (BC_0, RSER(5), bidir, X, 309, 0, Z), " & "307 (BC_1, *, controlr, 0), " & "306 (BC_0, TSYSCLK(5), bidir, X, 307, 0, PULL0)," & "305 (BC_1, *, controlr, 0), " & "304 (BC_0, RSYSCLK(5), bidir, X, 305, 0, PULL0)," & "303 (BC_1, *, controlr, 0), " & "302 (BC_0, RSIG(5), bidir, X, 303, 0, Z), " & "301 (BC_1, *, controlr, 0), " & "300 (BC_0, RCHBLK(5), bidir, X, 301, 0, Z), " & "299 (BC_1, *, controlr, 0), " & "298 (BC_0, TCHBLK(6), bidir, X, 299, 0, Z), " & "297 (BC_1, *, controlr, 0), " & "296 (BC_0, TCLK(6), bidir, X, 297, 0, Z), " & "295 (BC_1, *, controlr, 0), " & "294 (BC_0, TSER(6), bidir, X, 295, 0, Z), " & "293 (BC_1, *, controlr, 0), " & "292 (BC_0, TSYNC(6), bidir, X, 293, 0, Z), " & "291 (BC_1, *, controlr, 0), " & "290 (BC_0, TSIG(6), bidir, X, 291, 0, Z), " & "289 (BC_1, *, controlr, 0), " & "288 (BC_0, RSYNC(6), bidir, X, 289, 0, Z), " & "287 (BC_1, *, controlr, 0), " & "286 (BC_0, RMSYNC(6), bidir, X, 287, 0, Z), " & "285 (BC_1, *, controlr, 0), " & "284 (BC_0, RSER(6), bidir, X, 285, 0, Z), " & "283 (BC_1, *, controlr, 0), " & "282 (BC_0, TSYSCLK(6), bidir, X, 283, 0, PULL0)," & "281 (BC_1, *, controlr, 0), " & "280 (BC_0, RSYSCLK(6), bidir, X, 281, 0, PULL0)," & "279 (BC_1, *, controlr, 0), " & "278 (BC_0, RSIG(6), bidir, X, 279, 0, Z), " & "277 (BC_1, *, controlr, 0), " & "276 (BC_0, RCHBLK(6), bidir, X, 277, 0, Z), " & "275 (BC_1, *, controlr, 0), " & "274 (BC_0, TSYSCLK(1), bidir, X, 275, 0, Z), " & "273 (BC_1, *, controlr, 0), " & "272 (BC_0, RCHBLK(14), bidir, X, 273, 0, Z), " & "271 (BC_1, *, controlr, 0), " & "270 (BC_0, RSYSCLK(1), bidir, X, 271, 0, Z), " & "269 (BC_1, *, controlr, 0), " & "268 (BC_0, BTS, bidir, X, 269, 0, Z), " & "267 (BC_1, *, controlr, 0), " & "266 (BC_0, TX_ENABLE, bidir, X, 267, 0, Z), " & "265 (BC_1, *, controlr, 0), " & "264 (BC_0, RESETB, bidir, X, 265, 0, Z), " & "263 (BC_1, *, controlr, 0), " & "262 (BC_0, RCLK(5), bidir, X, 263, 0, Z), " & "261 (BC_1, *, controlr, 0), " & "260 (BC_0, RCLK(13), bidir, X, 261, 0, Z), " & "259 (BC_1, *, controlr, 0), " & "258 (BC_0, RCLK(6), bidir, X, 259, 0, Z), " & "257 (BC_1, *, controlr, 0), " & "256 (BC_0, RCLK(14), bidir, X, 257, 0, Z), " & "255 (BC_1, *, controlr, 0), " & "254 (BC_0, GPIO(6), bidir, X, 255, 0, Z), " & "253 (BC_1, *, controlr, 0), " & "252 (BC_0, SCAN_MODE, bidir, X, 253, 0, Z), " & "251 (BC_1, *, controlr, 0), " & "250 (BC_0, RCHBLK(8), bidir, X, 251, 0, Z), " & "249 (BC_1, *, controlr, 0), " & "248 (BC_0, RCHBLK(16), bidir, X, 249, 0, Z), " & "247 (BC_1, *, controlr, 0), " & "246 (BC_0, RSIG(8), bidir, X, 247, 0, Z), " & "245 (BC_1, *, controlr, 0), " & "244 (BC_0, RSIG(16), bidir, X, 245, 0, Z), " & "243 (BC_1, *, controlr, 0), " & "242 (BC_0, RCLK(7), bidir, X, 243, 0, Z), " & "241 (BC_1, *, controlr, 0), " & "240 (BC_0, RCLK(15), bidir, X, 241, 0, Z), " & "239 (BC_1, *, controlr, 0), " & "238 (BC_0, RCLK(8), bidir, X, 239, 0, Z), " & "237 (BC_1, *, controlr, 0), " & "236 (BC_0, RCLK(16), bidir, X, 237, 0, Z), " & "235 (BC_1, *, controlr, 0), " & "234 (BC_0, RSYSCLK(8), bidir, X, 235, 0, PULL0)," & "233 (BC_1, *, controlr, 0), " & "232 (BC_0, RSYSCLK(16), bidir, X, 233, 0, Z), " & "231 (BC_1, *, controlr, 0), " & "230 (BC_0, TSYSCLK(8), bidir, X, 231, 0, PULL0)," & "229 (BC_1, *, controlr, 0), " & "228 (BC_0, TSYSCLK(16), bidir, X, 229, 0, Z), " & "227 (BC_1, *, controlr, 0), " & "226 (BC_0, RSER(8), bidir, X, 227, 0, Z), " & "225 (BC_1, *, controlr, 0), " & "224 (BC_0, RSER(16), bidir, X, 225, 0, Z), " & "223 (BC_1, *, controlr, 0), " & "222 (BC_0, RMSYNC(8), bidir, X, 223, 0, Z), " & "221 (BC_1, *, controlr, 0), " & "220 (BC_0, RMSYNC(16), bidir, X, 221, 0, Z), " & "219 (BC_1, *, controlr, 0), " & "218 (BC_0, RSYNC(8), bidir, X, 219, 0, Z), " & "217 (BC_1, *, controlr, 0), " & "216 (BC_0, RSYNC(16), bidir, X, 217, 0, Z), " & "215 (BC_1, *, controlr, 0), " & "214 (BC_0, TCHBLK(15), bidir, X, 215, 0, Z), " & "213 (BC_1, *, controlr, 0), " & "212 (BC_0, BPCLK2, bidir, X, 213, 0, Z), " & "211 (BC_1, *, controlr, 0), " & "210 (BC_0, TCHBLK(10), bidir, X, 211, 0, Z), " & "209 (BC_1, *, controlr, 0), " & "208 (BC_0, TCLK(10), bidir, X, 209, 0, Z), " & "207 (BC_1, *, controlr, 0), " & "206 (BC_0, TSER(10), bidir, X, 207, 0, Z), " & "205 (BC_1, *, controlr, 0), " & "204 (BC_0, TSYNC(10), bidir, X, 205, 0, Z), " & "203 (BC_1, *, controlr, 0), " & "202 (BC_0, TSIG(10), bidir, X, 203, 0, Z), " & "201 (BC_1, *, controlr, 0), " & "200 (BC_0, RSYNC(10), bidir, X, 201, 0, Z), " & "199 (BC_1, *, controlr, 0), " & "198 (BC_0, RMSYNC(10), bidir, X, 199, 0, Z), " & "197 (BC_1, *, controlr, 0), " & "196 (BC_0, RSER(10), bidir, X, 197, 0, Z), " & "195 (BC_1, *, controlr, 0), " & "194 (BC_0, TSYSCLK(10), bidir, X, 195, 0, Z), " & "193 (BC_1, *, controlr, 0), " & "192 (BC_0, RSYSCLK(10), bidir, X, 193, 0, Z), " & "191 (BC_1, *, controlr, 0), " & "190 (BC_0, RSIG(10), bidir, X, 191, 0, Z), " & "189 (BC_1, *, controlr, 0), " & "188 (BC_0, RCHBLK(10), bidir, X, 189, 0, Z), " & "187 (BC_1, *, controlr, 0), " & "186 (BC_0, TCHBLK(9), bidir, X, 187, 0, Z), " & "185 (BC_1, *, controlr, 0), " & "184 (BC_0, TCLK(9), bidir, X, 185, 0, Z), " & "183 (BC_1, *, controlr, 0), " & "182 (BC_0, TSER(9), bidir, X, 183, 0, Z), " & "181 (BC_1, *, controlr, 0), " & "180 (BC_0, TSYNC(9), bidir, X, 181, 0, Z), " & "179 (BC_1, *, controlr, 0), " & "178 (BC_0, TSIG(9), bidir, X, 179, 0, Z), " & "177 (BC_1, *, controlr, 0), " & "176 (BC_0, RSYNC(9), bidir, X, 177, 0, Z), " & "175 (BC_1, *, controlr, 0), " & "174 (BC_0, RMSYNC(9), bidir, X, 175, 0, Z), " & "173 (BC_1, *, controlr, 0), " & "172 (BC_0, RSER(9), bidir, X, 173, 0, Z), " & "171 (BC_1, *, controlr, 0), " & "170 (BC_0, GPIO(7), bidir, X, 171, 0, Z), " & "169 (BC_1, *, controlr, 0), " & "168 (BC_0, GPIO(8), bidir, X, 169, 0, Z), " & "167 (BC_1, *, controlr, 0), " & "166 (BC_0, GPIO(9), bidir, X, 167, 0, Z), " & "165 (BC_1, *, controlr, 0), " & "164 (BC_0, GPIO(10), bidir, X, 165, 0, Z), " & "163 (BC_1, *, controlr, 0), " & "162 (BC_0, GPIO(11), bidir, X, 163, 0, Z), " & "161 (BC_1, *, controlr, 0), " & "160 (BC_0, GPIO(12), bidir, X, 161, 0, Z), " & "159 (BC_1, *, controlr, 0), " & "158 (BC_0, GPIO(13), bidir, X, 159, 0, Z), " & "157 (BC_1, *, controlr, 0), " & "156 (BC_0, GPIO(14), bidir, X, 157, 0, Z), " & "155 (BC_1, *, controlr, 0), " & "154 (BC_0, GPIO(15), bidir, X, 155, 0, Z), " & "153 (BC_1, *, controlr, 0), " & "152 (BC_0, GPIO(16), bidir, X, 153, 0, Z), " & "151 (BC_1, *, controlr, 0), " & "150 (BC_0, TCLK(15), bidir, X, 151, 0, Z), " & "149 (BC_1, *, controlr, 0), " & "148 (BC_0, TCLK(12), bidir, X, 149, 0, Z), " & "147 (BC_1, *, controlr, 0), " & "146 (BC_0, GPIO(1), bidir, X, 147, 0, Z), " & "145 (BC_1, *, controlr, 0), " & "144 (BC_0, GPIO(2), bidir, X, 145, 0, Z), " & "143 (BC_1, *, controlr, 0), " & "142 (BC_0, GPIO(3), bidir, X, 143, 0, Z), " & "141 (BC_1, *, controlr, 0), " & "140 (BC_0, TSER(15), bidir, X, 141, 0, Z), " & "139 (BC_1, *, controlr, 0), " & "138 (BC_0, TSIG(16), bidir, X, 139, 0, Z), " & "137 (BC_1, *, controlr, 0), " & "136 (BC_0, TSYNC(8), bidir, X, 137, 0, Z), " & "135 (BC_1, *, controlr, 0), " & "134 (BC_0, TSYNC(16), bidir, X, 135, 0, Z), " & "133 (BC_1, *, controlr, 0), " & "132 (BC_0, TSER(8), bidir, X, 133, 0, Z), " & "131 (BC_1, *, controlr, 0), " & "130 (BC_0, TSER(16), bidir, X, 131, 0, Z), " & "129 (BC_1, *, controlr, 0), " & "128 (BC_0, TCLK(8), bidir, X, 129, 0, Z), " & "127 (BC_1, *, controlr, 0), " & "126 (BC_0, TCLK(16), bidir, X, 127, 0, Z), " & "125 (BC_1, *, controlr, 0), " & "124 (BC_0, TSYNC(15), bidir, X, 125, 0, Z), " & "123 (BC_1, *, controlr, 0), " & "122 (BC_0, TCHBLK(16), bidir, X, 123, 0, Z), " & "121 (BC_1, *, controlr, 0), " & "120 (BC_0, RCHBLK(7), bidir, X, 121, 0, Z), " & "119 (BC_1, *, controlr, 0), " & "118 (BC_0, RCHBLK(15), bidir, X, 119, 0, Z), " & "117 (BC_1, *, controlr, 0), " & "116 (BC_0, RSIG(7), bidir, X, 117, 0, Z), " & "115 (BC_1, *, controlr, 0), " & "114 (BC_0, RSIG(15), bidir, X, 115, 0, Z), " & "113 (BC_1, *, controlr, 0), " & "112 (BC_0, RSYSCLK(7), bidir, X, 113, 0, PULL0)," & "111 (BC_1, *, controlr, 0), " & "110 (BC_0, RSYSCLK(15), bidir, X, 111, 0, Z), " & "109 (BC_1, *, controlr, 0), " & "108 (BC_0, TSYSCLK(7), bidir, X, 109, 0, PULL0)," & "107 (BC_1, *, controlr, 0), " & "106 (BC_0, TSYSCLK(15), bidir, X, 107, 0, Z), " & "105 (BC_1, *, controlr, 0), " & "104 (BC_0, RSER(7), bidir, X, 105, 0, Z), " & "103 (BC_1, *, controlr, 0), " & "102 (BC_0, RSER(15), bidir, X, 103, 0, Z), " & "101 (BC_1, *, controlr, 0), " & "100 (BC_0, RMSYNC(7), bidir, X, 101, 0, Z), " & "99 (BC_1, *, controlr, 0), " & "98 (BC_0, RMSYNC(15), bidir, X, 99, 0, Z), " & "97 (BC_1, *, controlr, 0), " & "96 (BC_0, A(13), bidir, X, 97, 0, Z), " & "95 (BC_1, *, controlr, 0), " & "94 (BC_0, RSYNC(15), bidir, X, 95, 0, Z), " & "93 (BC_1, *, controlr, 0), " & "92 (BC_0, TSIG(7), bidir, X, 93, 0, Z), " & "91 (BC_1, *, controlr, 0), " & "90 (BC_0, TSIG(15), bidir, X, 91, 0, Z), " & "89 (BC_1, *, controlr, 0), " & "88 (BC_0, TSYNC(7), bidir, X, 89, 0, Z), " & "87 (BC_1, *, controlr, 0), " & "86 (BC_0, TCHBLK(8), bidir, X, 87, 0, Z), " & "85 (BC_1, *, controlr, 0), " & "84 (BC_0, TSER(7), bidir, X, 85, 0, Z), " & "83 (BC_1, *, controlr, 0), " & "82 (BC_0, TSIG(8), bidir, X, 83, 0, Z), " & "81 (BC_1, *, controlr, 0), " & "80 (BC_0, TCLK(7), bidir, X, 81, 0, Z), " & "79 (BC_1, *, controlr, 0), " & "78 (BC_0, TCHBLK(7), bidir, X, 79, 0, Z), " & "77 (BC_1, *, controlr, 0), " & "76 (BC_0, A(0), bidir, X, 77, 0, Z), " & "75 (BC_1, *, controlr, 0), " & "74 (BC_0, A(1), bidir, X, 75, 0, Z), " & "73 (BC_1, *, controlr, 0), " & "72 (BC_0, A(2), bidir, X, 73, 0, Z), " & "71 (BC_1, *, controlr, 0), " & "70 (BC_0, A(3), bidir, X, 71, 0, Z), " & "69 (BC_1, *, controlr, 0), " & "68 (BC_0, A(4), bidir, X, 69, 0, Z), " & "67 (BC_1, *, controlr, 0), " & "66 (BC_0, A(5), bidir, X, 67, 0, Z), " & "65 (BC_1, *, controlr, 0), " & "64 (BC_0, A(6), bidir, X, 65, 0, Z), " & "63 (BC_1, *, controlr, 0), " & "62 (BC_0, A(7), bidir, X, 63, 0, Z), " & "61 (BC_1, *, controlr, 0), " & "60 (BC_0, A(8), bidir, X, 61, 0, Z), " & "59 (BC_1, *, controlr, 0), " & "58 (BC_0, A(9), bidir, X, 59, 0, Z), " & "57 (BC_1, *, controlr, 0), " & "56 (BC_0, A(10), bidir, X, 57, 0, Z), " & "55 (BC_1, *, controlr, 0), " & "54 (BC_0, A(11), bidir, X, 55, 0, Z), " & "53 (BC_1, *, controlr, 0), " & "52 (BC_0, A(12), bidir, X, 53, 0, Z), " & "51 (BC_1, *, controlr, 0), " & "50 (BC_0, RSYNC(7), bidir, X, 51, 0, Z), " & "49 (BC_1, *, controlr, 0), " & "48 (BC_0, BPCLK1, bidir, X, 49, 0, Z), " & "47 (BC_1, *, controlr, 0), " & "46 (BC_0, REFCLKIO, bidir, X, 47, 0, Z), " & "45 (BC_1, *, controlr, 0), " & "44 (BC_0, MCLK, bidir, X, 45, 0, Z), " & "43 (BC_1, *, controlr, 0), " & "42 (BC_0, TCHBLK(2), bidir, X, 43, 0, Z), " & "41 (BC_1, *, controlr, 0), " & "40 (BC_0, TCLK(2), bidir, X, 41, 0, Z), " & "39 (BC_1, *, controlr, 0), " & "38 (BC_0, TSER(2), bidir, X, 39, 0, Z), " & "37 (BC_1, *, controlr, 0), " & "36 (BC_0, TSYNC(2), bidir, X, 37, 0, Z), " & "35 (BC_1, *, controlr, 0), " & "34 (BC_0, TSIG(2), bidir, X, 35, 0, Z), " & "33 (BC_1, *, controlr, 0), " & "32 (BC_0, RSYNC(2), bidir, X, 33, 0, Z), " & "31 (BC_1, *, controlr, 0), " & "30 (BC_0, RMSYNC(2), bidir, X, 31, 0, Z), " & "29 (BC_1, *, controlr, 0), " & "28 (BC_0, RSER(2), bidir, X, 29, 0, Z), " & "27 (BC_1, *, controlr, 0), " & "26 (BC_0, TSYSCLK(2), bidir, X, 27, 0, PULL0)," & "25 (BC_1, *, controlr, 0), " & "24 (BC_0, RSYSCLK(2), bidir, X, 25, 0, PULL0)," & "23 (BC_1, *, controlr, 0), " & "22 (BC_0, RSIG(2), bidir, X, 23, 0, Z), " & "21 (BC_1, *, controlr, 0), " & "20 (BC_0, RCHBLK(2), bidir, X, 21, 0, Z), " & "19 (BC_1, *, controlr, 0), " & "18 (BC_0, TCHBLK(1), bidir, X, 19, 0, Z), " & "17 (BC_1, *, controlr, 0), " & "16 (BC_0, TCLK(1), bidir, X, 17, 0, Z), " & "15 (BC_1, *, controlr, 0), " & "14 (BC_0, TSER(1), bidir, X, 15, 0, Z), " & "13 (BC_1, *, controlr, 0), " & "12 (BC_0, TSYNC(1), bidir, X, 13, 0, Z), " & "11 (BC_1, *, controlr, 0), " & "10 (BC_0, TSIG(1), bidir, X, 11, 0, Z), " & "9 (BC_1, *, controlr, 0), " & "8 (BC_0, RSYNC(1), bidir, X, 9, 0, Z), " & "7 (BC_1, *, controlr, 0), " & "6 (BC_0, RMSYNC(1), bidir, X, 7, 0, Z), " & "5 (BC_1, *, controlr, 0), " & "4 (BC_0, RSER(1), bidir, X, 5, 0, Z), " & "3 (BC_1, *, controlr, 0), " & "2 (BC_0, GPIO(4), bidir, X, 3, 0, Z), " & "1 (BC_1, *, controlr, 0), " & "0 (BC_0, GPIO(5), bidir, X, 1, 0, Z) "; end ds26519_wrapper;