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产品详情

The MAX5868 evaluation kit (EV kit) contains a single MAX5868 high-performance interpolating and modulating 16-Bit, 4.96Gsps digital-to-analog converter (DAC) which can directly synthesize 500MHz of instantaneous bandwidth from DC to frequencies greater than 2GHz. The device is optimized for cable access and digital video broadcast applications and meets spectral emission requirements for a broad set of radio transmitters and modulators, including EPoC, DVB-T, DVB-T2, DVB-C2, ISDB-T, and DOCSIS 3.0/3.1. The MAX5868 EV kit provides a complete system for evaluating performance of the MAX5868 device, as well as development of a digital video solution.

The MAX5868 employs a source-synchronous 16-bit parallel LVDS data input interface. The input baseband I and Q signals are time-interleaved on a single parallel input port configured for double data rate clocking at up to 1240Mwps (620Mwps I and Q each). The device accepts data in word (16 bit), byte (8 bit), or nibble (4 bit) modes. The input data is aligned to the data clock supplied with the data. An input FIFO decouples the timing of the input interface from the DAC update clock domain. In addition, a parity input and parity flag interrupt output are available to ensure data integrity.

The MAX5868 EV kit also includes an on-board PLL-VCO (MAX2871) that provides the DAC update clock signal, CLKP/CLKN. The MAX5868EvkitSoftwareController provides all necessary controls to configure the MAX2871 for the desired DAC update rate from 100Msps to 5Gsps.

The EV kit includes Windows® 7/10-compatible software that provides a simple graphical user interface (GUI) for configuration of all the MAX5868 registers through the SPI interface, control of the Xilinx VC707 FPGA data source board, and temperature monitoring.

主要特征

  • Evaluates the MAX5868 RF DAC Performance, Capability, and Feature Set
  • Single 3.3V Input Voltage Supply
  • On-Board Clock Generation Module Employing MAX2871 VCO/PLL
  • Direct Interface with Xilinx® VC707 Data Source Board
  • Windows 7/10-Compatible Software
  • Optional On-Board SPI Interface Control for the MAX5868
  • On-Board SMBus Interface Control for the MAX6654 Temperature Sensor
  • Integrated GUI Controls for VC707 Operation
  • Proven 10-Layer PCB Design
  • Fully Assembled and Tested

应用/用途

  • 数字视频广播
  • 下行DOCSIS CMTS调制器
  • null
  • 同轴电缆以太网PON (EPoC)

技术文档

数据资料 Evaluation Kit for the MAX5868 Jul 23, 2019

设计与质量

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支持和培训

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参量

主要特征

  • Evaluates the MAX5868 RF DAC Performance, Capability, and Feature Set
  • Single 3.3V Input Voltage Supply
  • On-Board Clock Generation Module Employing MAX2871 VCO/PLL
  • Direct Interface with Xilinx® VC707 Data Source Board
  • Windows 7/10-Compatible Software
  • Optional On-Board SPI Interface Control for the MAX5868
  • On-Board SMBus Interface Control for the MAX6654 Temperature Sensor
  • Integrated GUI Controls for VC707 Operation
  • Proven 10-Layer PCB Design
  • Fully Assembled and Tested

应用/用途

  • 数字视频广播
  • 下行DOCSIS CMTS调制器
  • null
  • 同轴电缆以太网PON (EPoC)

描述

The MAX5868 evaluation kit (EV kit) contains a single MAX5868 high-performance interpolating and modulating 16-Bit, 4.96Gsps digital-to-analog converter (DAC) which can directly synthesize 500MHz of instantaneous bandwidth from DC to frequencies greater than 2GHz. The device is optimized for cable access and digital video broadcast applications and meets spectral emission requirements for a broad set of radio transmitters and modulators, including EPoC, DVB-T, DVB-T2, DVB-C2, ISDB-T, and DOCSIS 3.0/3.1. The MAX5868 EV kit provides a complete system for evaluating performance of the MAX5868 device, as well as development of a digital video solution.

The MAX5868 employs a source-synchronous 16-bit parallel LVDS data input interface. The input baseband I and Q signals are time-interleaved on a single parallel input port configured for double data rate clocking at up to 1240Mwps (620Mwps I and Q each). The device accepts data in word (16 bit), byte (8 bit), or nibble (4 bit) modes. The input data is aligned to the data clock supplied with the data. An input FIFO decouples the timing of the input interface from the DAC update clock domain. In addition, a parity input and parity flag interrupt output are available to ensure data integrity.

The MAX5868 EV kit also includes an on-board PLL-VCO (MAX2871) that provides the DAC update clock signal, CLKP/CLKN. The MAX5868EvkitSoftwareController provides all necessary controls to configure the MAX2871 for the desired DAC update rate from 100Msps to 5Gsps.

The EV kit includes Windows® 7/10-compatible software that provides a simple graphical user interface (GUI) for configuration of all the MAX5868 registers through the SPI interface, control of the Xilinx VC707 FPGA data source board, and temperature monitoring.

技术文档

数据资料 Evaluation Kit for the MAX5868 Jul 23, 2019

支持和培训

在Maxim的知识库中搜索您所需的答案。

过滤搜索

Maxim专业的应用工程师团队也可以为您解答技术问题,请 访问Maxim的 支持中心