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The MAX3676 is a complete clock-recovery and data-retiming IC incorporating a limiting amplifier. It is intended for 622Mbps SDH/SONET applications and operates from a single +3.3V supply.
The MAX3676 is designed for both section-regenerator and terminal-receiver applications in OC12/STM-4 transmission systems. Its jitter performance exceeds all SONET/SDH specifications.
The MAX3676 has two differential input amplifiers: one accepts positive-referenced emitter-coupled logic (PECL) levels, while the other accepts small-signal analog levels. The analog inputs access the limiting amplifier stage, which provides both a received-signal-strength indicator (RSSI) and a programmable-threshold loss-of-power (LOP) monitor. Selecting the PECL amplifier disables the limiting amplifier, conserving power. A loss-of-lock (LOL) monitor is also incorporated as part of the fully integrated phase-locked loop (PLL).
The MAX3676 is designed for both section-regenerator and terminal-receiver applications in OC12/STM-4 transmission systems. Its jitter performance exceeds all SONET/SDH specifications.
The MAX3676 has two differential input amplifiers: one accepts positive-referenced emitter-coupled logic (PECL) levels, while the other accepts small-signal analog levels. The analog inputs access the limiting amplifier stage, which provides both a received-signal-strength indicator (RSSI) and a programmable-threshold loss-of-power (LOP) monitor. Selecting the PECL amplifier disables the limiting amplifier, conserving power. A loss-of-lock (LOL) monitor is also incorporated as part of the fully integrated phase-locked loop (PLL).
主要特征
- Single +3.3V or +5.0V Power Supply
- Exceeds ITU/Bellcore SDH/SONET Regenerator Specifications
- Low Power: 237mW at +3.3V
- Selectable Data Inputs, Differential PECL or Analog
- Received-Signal-Strength Indicator
- Loss-of-Power and Loss-of-Lock Monitors
- Differential PECL Clock and Data Outputs
- No External Reference Clock Required
应用/用途
- 上/下路复用器
- ATM交换
- 数字交叉连接
- SDH/SONET接入节点
- SDH/SONET接收器与再生器
技术文档
| 数据资料 | 622Mbps、3.3V时钟恢复与数据再定时IC，带有限幅放大器 | Mar 02, 2009 |
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参量
主要特征
- Single +3.3V or +5.0V Power Supply
- Exceeds ITU/Bellcore SDH/SONET Regenerator Specifications
- Low Power: 237mW at +3.3V
- Selectable Data Inputs, Differential PECL or Analog
- Received-Signal-Strength Indicator
- Loss-of-Power and Loss-of-Lock Monitors
- Differential PECL Clock and Data Outputs
- No External Reference Clock Required
应用/用途
- 上/下路复用器
- ATM交换
- 数字交叉连接
- SDH/SONET接入节点
- SDH/SONET接收器与再生器
描述
The MAX3676 is a complete clock-recovery and data-retiming IC incorporating a limiting amplifier. It is intended for 622Mbps SDH/SONET applications and operates from a single +3.3V supply.
The MAX3676 is designed for both section-regenerator and terminal-receiver applications in OC12/STM-4 transmission systems. Its jitter performance exceeds all SONET/SDH specifications.
The MAX3676 has two differential input amplifiers: one accepts positive-referenced emitter-coupled logic (PECL) levels, while the other accepts small-signal analog levels. The analog inputs access the limiting amplifier stage, which provides both a received-signal-strength indicator (RSSI) and a programmable-threshold loss-of-power (LOP) monitor. Selecting the PECL amplifier disables the limiting amplifier, conserving power. A loss-of-lock (LOL) monitor is also incorporated as part of the fully integrated phase-locked loop (PLL).
The MAX3676 is designed for both section-regenerator and terminal-receiver applications in OC12/STM-4 transmission systems. Its jitter performance exceeds all SONET/SDH specifications.
The MAX3676 has two differential input amplifiers: one accepts positive-referenced emitter-coupled logic (PECL) levels, while the other accepts small-signal analog levels. The analog inputs access the limiting amplifier stage, which provides both a received-signal-strength indicator (RSSI) and a programmable-threshold loss-of-power (LOP) monitor. Selecting the PECL amplifier disables the limiting amplifier, conserving power. A loss-of-lock (LOL) monitor is also incorporated as part of the fully integrated phase-locked loop (PLL).
技术文档
| 数据资料 | 622Mbps、3.3V时钟恢复与数据再定时IC，带有限幅放大器 | Mar 02, 2009 |
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