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2x4通道、同时采样、14位DAS

首款14位、8通道、同时采样ADC,用于工业产品

产品详情

主要特征

Parametric specs for Precision ADCs (< 5Msps)
Resolution (bits) (ADC) 14
# Input Channels 8
Conv. Rate (ksps) (max) 250
Data Bus µP/14
ADC Architecture SAR
Diff/S.E. Input S.E. Only
Internal VREF (V) (nominal) 2.5
External VREF (V) (min) 2.25
External VREF (V) (max) 2.75
Bipolar VIN (±V) (max) 2.5
INL (±LSB) 2
Package/Pins SSOP/36
Budgetary
Price (See Notes)
21.08
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参量

Parametric specs for Precision ADCs (<u><</u> 5Msps)
Resolution (bits) (ADC) 14
# Input Channels 8
Conv. Rate (ksps) (max) 250
Data Bus µP/14
ADC Architecture SAR
Diff/S.E. Input S.E. Only
Internal VREF (V) (nominal) 2.5
External VREF (V) (min) 2.25
External VREF (V) (max) 2.75
Bipolar VIN (±V) (max) 2.5
INL (±LSB) 2
Package/Pins SSOP/36
Budgetary
Price (See Notes)
21.08

主要特征

  • Four Simultaneous-Sampling T/H Amplifiers with Two Multiplexed Inputs (eight single-ended inputs total)
  • 3µs Conversion Time per Channel
  • Throughput:
    • 250ksps (1 channel)
    • 142ksps (2 channels)
    • 100ksps (3 channels)
    • 76ksps (4 channels)
  • Input Range:
    • ±5V (MAX125)
    • ±2.5V (MAX126)
  • Fault-Protected Input Multiplexer (±17V)
  • ±5V Supplies
  • Internal +2.5V or External Reference Operation
  • Programmable On-Board Sequencer
  • High-Speed Parallel DSP Interface

应用/用途

  • 数字信号处理(DSP)
  • 多相电机控制
  • 功率因数监视
  • 电网同步
  • 振动与波形分析

描述

The MAX125/MAX126 are high-speed, multichannel, 14-bit data-acquisition systems (DAS) with simultaneous track/holds (T/Hs). These devices contain a 14-bit, 3µs, successive-approximation analog-to-digital converter (ADC), a +2.5V reference, a buffered reference input, and a bank of four simultaneous-sampling T/H amplifiers that preserve the relative phase information of the sampled inputs. The MAX125/MAX126 have two multiplexed inputs for each T/H, allowing a total of eight inputs. In addition, the converter is overvoltage tolerant to ±17V; a fault condition on any channel will not harm the IC. Available input ranges are ±5V (MAX125) and ±2.5V (MAX126).

An on-board sequencer converts one to four channels per active-low CONVST pulse. In the default mode, one T/H output (CH1A) is converted. An interrupt signal (active-low INT) is provided after the last conversion is complete. Convert two, three, or four channels by reprogramming the MAX125/MAX126 through the bidirectional parallel interface. Once programmed, the MAX125/MAX126 continue to convert the specified number of channels per active-low CONVST pulse until they are reprogrammed. The channels are converted sequentially, beginning with CH1. The INT signal always follows the end of the last conversion in a conversion sequence. The ADC converts each assigned channel in 3µs and stores the result in an internal 14x4 RAM. Upon completion of the conversions, data can be accessed by applying successive pulses to the active-low RD pin. Four successive reads access four data words sequentially.

The parallel interface's data-access and bus-release timing specifications are compatible with most popular digital signal processors and 16-bit/32-bit microprocessors, so the MAX125/MAX126 conversion results can be accessed without resorting to wait states.

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MAX125、MAX126:典型工作电路 MAX125、MAX126:典型工作电路 Zoom icon

Technical Docs

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在Maxim的知识库中搜索技术问题的答案

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Maxim的专业工程师团队也会为您解答相应的技术问题,请访问Maxim的 支持中心