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500ksps、12位ADC,带有采样/保持和电压基准

产品详情

主要特征

Parametric specs for Precision ADCs (< 5Msps)
Resolution (bits) (ADC) 12
# Input Channels 1
Conv. Rate (ksps) (max) 333
Data Bus µP/12
ADC Architecture SAR
Diff/S.E. Input S.E. Only
Internal VREF (V) (nominal) 5
Bipolar VIN (±V) (max) 5
INL (±LSB) 1
Package/Pins PDIP/24
SOIC (W)/24
SSOP/24
Budgetary
Price (See Notes)
18.68
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参量

Parametric specs for Precision ADCs (<u><</u> 5Msps)
Resolution (bits) (ADC) 12
# Input Channels 1
Conv. Rate (ksps) (max) 333
Data Bus µP/12
ADC Architecture SAR
Diff/S.E. Input S.E. Only
Internal VREF (V) (nominal) 5
Bipolar VIN (±V) (max) 5
INL (±LSB) 1
Package/Pins PDIP/24
SOIC (W)/24
SSOP/24
Budgetary
Price (See Notes)
18.68

主要特征

  • 12-Bit Resolution
  • No Missing Codes Over Temperature
  • 20ppm/°C -5V Internal Reference
  • 1.6µs Conversion Time/500ksps Throughput (MAX120)
  • 2.6µs Conversion Time/333ksps Throughput (MAX122)
  • Low Noise and Distortion:
    • 70dB Minimum SINAD;
    • -70dB Max THD (MAX122)
  • Low Power Dissipation: 210mW
  • Separate Track/Hold Control Input
  • Continuous-Conversion Mode Available
  • ±5V Input Range, Overvoltage Tolerant to ±15V
  • 24-Pin Narrow DIP, Wide SO and SSOP Packages

应用/用途

描述

The MAX120/MAX122 complete, BiCMOS, sampling 12-bit analog-to-digital converters (ADCs) combine an on-chip track/hold (T/H) and a low-drift voltage reference with fast conversion speeds and low-power consumption. The T/H’s 350ns acquisition time combined with the MAX120’s 1.6µs conversion time results in throughput rates as high as 500k samples per second (ksps). Throughput rates of 333ksps are possible with the 2.6μs conversion time of the MAX122.

The MAX120/MAX122 accept analog input voltages from -5V to +5V. The only external components needed are decoupling capacitors for the power-supply and reference voltages. The MAX120 operates with clocks in the 0.1MHz to 8MHz frequency range. The MAX122 accepts 0.1MHz to 5MHz clock frequencies.

The MAX120/MAX122 employ a standard microprocessor (µP) interface. Three-state data outputs are configured to operate with 12-bit data buses. Data-access and bus-release timing specifications are compatible with most popular µPs without resorting to wait states. In addition, the MAX120/MAX122 can interface directly to a first-in, first-out (FIFO) buffer, virtually eliminating µP interrupt overhead. All logic inputs and outputs are TTL/CMOS compatible. For applications requiring a serial interface, refer to the MAX121.

简化框图

MAX120、MAX122:功能框图 MAX120、MAX122:功能框图 Zoom icon

技术文档

支持和培训

在Maxim的知识库中搜索技术问题的答案

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Maxim的专业工程师团队也会为您解答相应的技术问题,请访问Maxim的 支持中心