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主要特征
应用/用途
Parametric specs for Precision ADCs (< 5Msps)
Resolution (bits) (ADC) | 12 |
# Input Channels | 8 |
Conv. Rate (ksps) (max) | 116 |
Data Bus | µP/12 |
ADC Architecture | SAR |
Diff/S.E. Input | S.E. Only |
Internal VREF (V) (nominal) | 2.5 |
External VREF (V) (min) | 2.4 |
External VREF (V) (max) | 2.6 |
Bipolar VIN (±V) (max) | 5 |
INL (±LSB) | 0.6 |
Package/Pins | SSOP/36 |
Budgetary Price (See Notes) | 12.53 |
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Technical Docs
数据资料 | 2x4通道、同时采样、12位ADC | Feb 26, 2001 | |
应用笔记 | ADCs for Simultaneous Sampling |
参量
Parametric specs for Precision ADCs (<u><</u> 5Msps)
Resolution (bits) (ADC) | 12 |
# Input Channels | 8 |
Conv. Rate (ksps) (max) | 116 |
Data Bus | µP/12 |
ADC Architecture | SAR |
Diff/S.E. Input | S.E. Only |
Internal VREF (V) (nominal) | 2.5 |
External VREF (V) (min) | 2.4 |
External VREF (V) (max) | 2.6 |
Bipolar VIN (±V) (max) | 5 |
INL (±LSB) | 0.6 |
Package/Pins | SSOP/36 |
Budgetary Price (See Notes) | 12.53 |
主要特征
- Four Simultaneous-Sampling T/H Amplifiers with Two Multiplexed Inputs (Eight Single-Ended Inputs Total)
- 2µs Conversion Time per Channel
- Throughput:
- 390ksps (1 Channel)
- 218ksps (2 Channels)
- 152ksps (3 Channels)
- 116ksps (4 Channels)
- Input Range: ±5V (MAX115)
- ±2.5V (MAX116)
- Fault-Protected Input Multiplexer (±17V)
- Internal +2.5V or External Reference Operation
- Programmable On-Board Sequencer
- High-Speed Parallel DSP Interface
- Internal 10MHz Clock
应用/用途
- 水电气表自动抄表
- 汽车ABS
- 工业传感器发送器/变送器
- 电机及运动控制
- 可编程逻辑控制器
描述
The MAX115/MAX116 are high-speed, multichannel, 12-bit data-acquisition systems (DAS) with simultaneous track/holds (T/Hs). These devices contain a 12-bit, 2µs, successive-approximation analog-to-digital converter (ADC), a +2.5V reference, a buffered reference input, and a bank of four simultaneous-sampling T/H amplifiers that preserve the relative phase information of the sampled inputs. The MAX115/MAX116 have two multiplexed inputs for each T/H, allowing a total of eight inputs. In addition, the converter is overvoltage tolerant to ±17V. A fault condition on any channel will not damage the IC. Available input ranges are ±5V (MAX115) and ±2.5V (MAX116).
The parallel interface's data access and bus release timing specifications are compatible with most popular digital signal processors and 16-bit/32-bit microprocessors. The MAX115/MAX116 conversion results can be accessed without resorting to wait-states.
The parallel interface's data access and bus release timing specifications are compatible with most popular digital signal processors and 16-bit/32-bit microprocessors. The MAX115/MAX116 conversion results can be accessed without resorting to wait-states.
Technical Docs
数据资料 | 2x4通道、同时采样、12位ADC | Feb 26, 2001 | |
应用笔记 | ADCs for Simultaneous Sampling |