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主要特征
应用/用途
Parametric specs for Precision ADCs (< 5Msps)
Resolution (bits) (ADC) | 14 |
# Input Channels | 2 |
Conv. Rate (ksps) (max) | 2000 |
Data Bus | SPI |
ADC Architecture | SAR |
Diff/S.E. Input | Diff. Only |
Internal VREF (V) (nominal) | 2.5 |
External VREF (V) (min) | 2.5 |
External VREF (V) (max) | 5 |
Unipolar VIN (V) (max) | 5 |
INL (±LSB) | 1 |
Package/Pins | TDFN/16 |
Budgetary Price (See Notes) | 5.82 |
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参量
Parametric specs for Precision ADCs (<u><</u> 5Msps)
Resolution (bits) (ADC) | 14 |
# Input Channels | 2 |
Conv. Rate (ksps) (max) | 2000 |
Data Bus | SPI |
ADC Architecture | SAR |
Diff/S.E. Input | Diff. Only |
Internal VREF (V) (nominal) | 2.5 |
External VREF (V) (min) | 2.5 |
External VREF (V) (max) | 5 |
Unipolar VIN (V) (max) | 5 |
INL (±LSB) | 1 |
Package/Pins | TDFN/16 |
Budgetary Price (See Notes) | 5.82 |
Parametric specs for Precision ADCs (<u><</u> 5Msps)
Resolution (bits) (ADC) | 14 |
# Input Channels | 2 |
Conv. Rate (ksps) (max) | 2000 |
Data Bus | SPI |
ADC Architecture | SAR |
Diff/S.E. Input | Diff. Only |
Internal VREF (V) (nominal) | 2.5 |
External VREF (V) (min) | 2.5 |
External VREF (V) (max) | 5 |
Unipolar VIN (V) (max) | 5 |
INL (±LSB) | 1 |
Package/Pins | TDFN/16 |
Budgetary Price (See Notes) | 5.82 |
主要特征
- 微小16引脚、3mm x 2mm、Ultra TDFN封装
- 高达2Msps吞吐率
- 两个同时采样ADC核心
- 2.5V集成基准和基准缓冲器
- 两路数据输出,分别用于两个同时采样ADC
- No Overhead Clock Cycles; 12/14/16 Clock Cycles for 12-/14-/16-Bit Result
- ±VREF平衡、差分输入范围
应用/用途
- 电机中电流检测
- 编码器
- LVDT
- PLC
- 分解器
描述
MAX11192为双通道SAR ADC,2Msps同时采样、12位分辨率以及差分输入。器件采用微小16引脚、3mm x 2mm ultra TDFN封装,ADC提供优异的静态和动态性能,采用3.0V至5.25V电源电压工作。集成基准进一步减小电路板面积和元件数量。
MAX11192的SNR为73dB (最小值)、THD为-108dB(典型值),INL小于±0.5LSB,无失码。SPI兼容串行接口包括每个通道的独立数据输出。技术指标适用于-40°C至+125°C扩展级温度范围。