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主要特征
应用/用途
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Technical Docs
数据资料 | 双路、6位、400Msps ADC,带有片上宽带输入放大器 | May 30, 2001 | |
应用笔记 | 以1Gsps高速捕捉信号的ADC | ||
设计指南 | 高速模数转换器(ADC)的INL/DNL测量 | ||
设计指南 | Design a Low-Jitter Clock for High-Speed Data Converters |
主要特征
- Two Matched 6-Bit, 400Msps ADCs
- Excellent Dynamic Performance
- 36.7dB SINAD at fIN ≈ 125MHz and
- fCLK ≈ 400MHz
- Typical INL and DNL: ±0.25LSB
- Channel-to-Channel Phase Matching: ±0.2°
- Channel-to-Channel Gain Matching: ±0.04dB
- 6:12 Demultiplexer reduces the Data Rates to 200MHz
- Low Error Rate: 1016 Metastable States at 400Msps
- LVDS Digital Outputs in Two's Complement Format
应用/用途
- 通信系统
- 测试仪表
- VSAT接收器
- 无线局域网(WLAN)
描述
The MAX107 is a dual, 6-bit, analog-to-digital converter (ADC) designed to allow fast and precise digitizing of in-phase (I) and quadrature (Q) baseband signals. The MAX107 converts the analog signals of both I and Q components to digital outputs at 400Msps while achieving a signal-to-noise ratio (SNR) of typically 37dB with an input frequency of 125MHz, and an integral nonlinearity (INL) and differential nonlinearity (DNL) of ±0.25 LSB. The MAX107 analog input preamplifiers feature a 400MHz, -0.5dB, and a 1.5GHz, -3dB analog input bandwidth. Matching channel-to-channel performance is typically 0.04dB gain, 0.1LSB offset, and 0.2 degrees phase. Dynamic performance is 36.7dB signal-to-noise plus distortion (SINAD) with a 125MHz analog input signal and a sampling speed of 400MHz. A fully differential comparator design and encoding circuits reduce out-of-sequence errors, and ensure excellent metastable performance of only one error per 1016 clock cycles.
In addition, the MAX107 provides LVDS digital outputs with an internal 6:12 demultiplexer that reduces the output data rate to one-half the sample clock rate. Data is output in two's complement format. The MAX107 operates from a +5V analog supply and the LVDS output ports operate at +3.3V. The data converter's typical power dissipation is 2.6W. The device is packaged in an 80-pin, TQFP package with exposed paddle, and is specified for the extended (-40°C to +85°C) temperature range. For a higher-speed, 800Msps version of the MAX107, please refer to the MAX105 data sheet.
In addition, the MAX107 provides LVDS digital outputs with an internal 6:12 demultiplexer that reduces the output data rate to one-half the sample clock rate. Data is output in two's complement format. The MAX107 operates from a +5V analog supply and the LVDS output ports operate at +3.3V. The data converter's typical power dissipation is 2.6W. The device is packaged in an 80-pin, TQFP package with exposed paddle, and is specified for the extended (-40°C to +85°C) temperature range. For a higher-speed, 800Msps version of the MAX107, please refer to the MAX105 data sheet.
Technical Docs
数据资料 | 双路、6位、400Msps ADC,带有片上宽带输入放大器 | May 30, 2001 | |
应用笔记 | 以1Gsps高速捕捉信号的ADC | ||
设计指南 | 高速模数转换器(ADC)的INL/DNL测量 | ||
设计指南 | Design a Low-Jitter Clock for High-Speed Data Converters |