The system energy manager is a highly integrated microcontroller that provides several key features for systems including key scanning and control, battery and power management, as well as two 2-Wire serial I/O Ports. It incorporates the Dallas 8051-compatible high-speed microcontroller core which has been redesigned to eliminate wasted clock and memory cycles. Every standard 8051 instruction is executed between 1.5 and 3 times faster than the original for the same crystal speed. Looking at it another way, the high-speed core achieves the same throughput as a standard 8051 while using much less power as a result of fewer required clock cycles. As a result, the firmware can easily support many tasks required by mobile systems within a single component.

The controller is designed to off-load battery and power management tasks from the host CPU and thereby make possible an efficient solution for systems. In addition to the microcontroller core, it incorporates an 8-channel, 10-bit A/D converter with external reference so that its firmware can perform battery management tasks without burdening the host CPU. A four-channel 8-bit pulse-width modulator allows digital control of functions such as LCD contrast and brightness. An 8-bit port is provided for key scan inputs. A total of 88 parallel I/O pins are available for key scanning, system configuration, and power management control.

The system energy manager scans a key matrix and interfaces to the host CPU via an 8042-compatible port. The benefits of sophisticated power management and permanently powered functions are thereby attained without adding to the system's chip count.

Two 2-wire, bi-directional serial buses are incorporated to facilitate the management of slave peripheral devices on the motherboard, such as digital temperature sensors and potentiometers, and to support external low-speed I/O devices such as monitor configuration channels, pen tablets, and joysticks.

Because a direct interface to the X-bus is provided, the controller is not dependent on a particular core logic chip or chip set. Independent chip select inputs for the keyboard controller, power management #1, and power management #2 registers are provided.
DS80CH11:引脚分配 DS80CH11:引脚分配 放大+


  • High speed 80C32 compatible core:
    • High performance 4 clocks/machine cycles (8032 = 12)
    • Low Power: typically 1/3 power for equivalent 8032 throughput
    • Maximum clock speed up to 25MHz at 5.0V
    • Ultra-low stop mode power (typ. 1uA) "IDLE" mode (typ. 10mA)
    • Multiple wake-up sources from STOP including key scan, 2-wire, host I/F, or external interrupt
    • Three 16-bit timers, 1 serial port
    • 256-byte scratchpad
    • 256 bytes MOVX RAM
  • Keyboard Control:
    • Replaces 8042 and key scan microcontroller
    • 2 Parallel I/O ports for key scan outputs
    • One interrupt-driven 8-bit input port to initiate key-scan sequence
  • Input/Output:
    • Total of eleven 8-bit I/O ports; all pins can individually programmed to serve as general purpose digital input/output.
    • 8-bit port supports one or more special functions:
      • Port 0, 2, 3: external program/data memory interface
      • Port 1, 3: UART, 2-Wire serial, timers, external interrupt I/O.
      • Port 4, 8, 9: Key scan input/output
      • Port 5: A/D inputs
      • Port 6: PWM Outputs
      • Port 7: activity monitor, LED control
      • Port 10: GPIO
  • Analog input/output:
    • Eight-channel, 10-bit A/D with power down mode supports charging NiMH rechargeable cells
    • 4-channel, 8-bit PWM supports LCD brightness and contrast control
  • 2-Wire bi-directional serial buses
    • Master/slave multi-drop operation
    • Manages on-board slaves or external I/O devices
  • Power Control
    • Generates system power on reset
    • Programmable power down pin states


应用笔记 4427 Demonstrating Green Technology with Apples, Oranges, Lemons, and Limes


产品可靠性报告: DS80CH11.pdf 
型号   生产流程   工艺   样本量   不合格   FIT @ 25°C   FIT @ 55°C  

备注: 通过技术手段对故障率进行汇总,并映射到相关的材料部件号。 故障率与被测件的数量密切相关。

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