Tiny, Cost-Effective, Plug-and-Play Digital Class-D Amplifier

 

器件号	Replacement	Explanation

说明

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The MAX98360A/B/C/D is an easy-to-use, low-cost, digital pulse-code modulation (PCM) input Class-D amplifier that provides industry-leading, Class-AB audio performance with Class-D efficiency. The digital audio interface automatically recognizes different PCM and TDM clocking schemes which eliminates the need for I²C programming. Simply supply power, LRCLK, BCLK, and digital audio to generate audio. Furthermore, a novel pinout allows customers to use the cost-effective WLP package with no need for expensive vias.

The digital audio interface is highly flexible. The devices support I²S, left-justified, and 8-channel time division multiplexed (TDM) data formats. The digital audio interface accepts 8kHz, 16kHz, 32kHz, 44.1kHz, 48kHz, 88.2kHz, and 96kHz sample rates. Data words can be 16-bit, 24-bit, or 32-bit in I²S and left-justified modes and 16-bit or 32-bit in TDM mode.

Digital audio interface input thresholds are ideal for interfacing to 1.2V and 1.8V logic. The devices can tolerate logic input voltages up to 5.5V.

The MAX98360A and MAX98360B have fast 1ms turn-on times while the MAX98360C and MAX98360D ramp the volume over 13ms during turn-on and turn-off.

The devices eliminate the need for the external MCLK signal that is typically used for PCM communication. This reduces EMI and possible board coupling issues in addition to reducing the size and pin count. The devices also feature a very high wideband jitter tolerance (12ns, typ) on BCLK and LRCLK to provide robust operation.

Active emissions-limiting, edge-rate limiting, and overshoot control circuitry greatly reduce EMI. A filterless spread-spectrum modulation scheme eliminates the need for output filtering found in traditional Class-D devices and reduces the component count of the solution.

The devices are specified over the -40°C to +85°C temperature range.

MAX98360 Version Management

	Ramping		Frame Sync Pulse on LRCLK		50% Duty Cycle on LRCLK
	Turn-On/Off Ramp	Start-Up Time	Format	BCLK Active Edge	Format	BCLK Active Edge
MAX98360A	Ramp Disabled	1ms	TDM	rising	I2S	rising
MAX98360B	Ramp Disabled	1ms	TDM	falling	LJ	rising
MAX98360C	Ramp Enabled	13ms	TDM	rising	I2S	rising
MAX98360D	Ramp Enabled	13ms	TDM	falling	LJ	rising

MAX98360A, MAX98360B, MAX98360C, MAX98360D: Functional Diagram 放大+

关键特性

• Simple Plug-and-Play Design
• Single-Supply Operation (2.5V to 5.5V)
• 3.2W Output Power into 4Ω at 5V
• 2.2mA Quiescent Current
• 1ms Turn-On Time (for MAX98360A and MAX98360B)
• 92% Efficiency (R_L = 8Ω, THD+N = 10%)
• 10μV_RMS Output Noise
• 110dB Dynamic Range
• Low 0.009% THD+N at 1kHz
• No MCLK Required
• Sample Rates of 8kHz to 96kHz
• Supports Left, Right, or (Left/2 + Right/2) Output in I²S and Left-Justified Modes
• Sophisticated Edge Rate Control Enables Filterless Class-D Outputs
• 81dB PSRR at 217Hz
• 1.5μA Standby Current Allows Elimination of GPIO for EN Pin
• Low RF Susceptibility Rejects TDMA Noise from GSM Radios
• Class-D Switching Frequency Trimmed to 5% for Better EMI Planning
• Extensive Click-and-Pop Reduction Circuitry
• Robust Short-Circuit and Thermal Protection
• Available in Space-Saving Package: 9-Pin WLP (0.4mm Pitch) or 10-Pin FC2QFN (0.5mm Pitch)
• 3.69mm² Solution Size for WLP With A Single Bypass Capacitor

应用

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