The DS1020 is an 8-bit programmable delay line that reproduces an input logic state at the output after a user-programmed delay. Delays can be varied over 256 steps with resolutions of 0.15ns, 0.25ns, 0.50ns, 1.0ns, or 2.0ns (see table). Total delays range from an inherent 10ns minimum delay to a maximum 520ns. The DS1020 is programmed over the 3-wire serial port or the 8-pin parallel port. The DS1020 is TTL- and CMOS-compatible, and capable of driving up to ten 74LS-type loads. Both leading- and trailing-edge accuracy are specified.

The DS1020 is an effective, economical solution to the designer working with the complex timing requirements of mismatched ASICs or other components, or with the strict timing tolerances of increasing system clock rates. With the DS1020's programmable outputs, the user can precisely adjust timing to application needs and improve system performance. Innovative circuit designs and factory laser or EPROM trimming enhance accuracy without the need for external components, saving cost and space.
DS1020,DS1020-100:功能原理框图 DS1020,DS1020-100:功能原理框图 放大+


  • All-silicon time delay
  • Models with 0.15ns, 0.25ns, 0.5ns, 1ns, and 2ns steps
  • Programmable using 3-wire serial port or 8-bit parallel port
  • Leading and trailing edge accuracy
  • Auto-insertable, low profile
  • Low-power CMOS with TTL compatibility
  • Vapor phase, IR, and wave solderable
申请可靠性报告: DS1020-100 
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备注: 通过技术手段对故障率进行汇总,并映射到相关的材料部件号。 故障率与被测件的数量密切相关。

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