DS1005

5抽头硅延迟线


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说明

The DS1005 5-Tap Silicon Delay Line reproduces an input logic state at the output after a fixed delay at five equally spaced taps, ranging from 12ns to 250ns. (See table.) Delay accuracy is characterized at ±3% or ±2ns (whichever is greater). Leading and trailing edges are reproduced with equal precision. Each tap is capable of driving up to ten 74LS loads.

By enabling precise timing adjustments, Dallas Silicon Delay Lines improve system performance. They provide an effective, economical solution to the designer working with the complex timing requirements of mismatched ASICs or other components, or with the strict timing tolerances of increasing system clock rates. Each delay line die is laser-optimized and molded into an auto-insertable DIP or space-saving SOIC package.

关键特性

  • All-silicon timing delay circuit
  • 5 taps, equally spaced
  • Delay tolerance +2ns or ±3%, whichever is greater
  • Leading and trailing edge accuracy
  • Low-power CMOS with TTL compatibility
  • Vapor phase, IR, and wave-solderability

质量和环境数据

产品可靠性报告: DS1005.pdf 
无铅封装的锡(Sn)晶须报告
型号   生产流程   工艺   样本量   不合格   FIT @ 25°C   FIT @ 55°C  

备注: 通过技术手段对故障率进行汇总,并映射到相关的材料部件号。 故障率与被测件的数量密切相关。

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