说明 The DS1005 5-Tap Silicon Delay Line reproduces an input logic state at the output after a fixed delay at five equally spaced taps, ranging from 12ns to 250ns. (See table.) Delay accuracy is characterized at ±3% or ±2ns (whichever is greater). Leading and trailing edges are reproduced with equal precision. Each tap is capable of driving up to ten 74LS loads.
By enabling precise timing adjustments, Dallas Silicon Delay Lines improve system performance. They provide an effective, economical solution to the designer working with the complex timing requirements of mismatched ASICs or other components, or with the strict timing tolerances of increasing system clock rates. Each delay line die is laser-optimized and molded into an auto-insertable DIP or space-saving SOIC package.