关键词: input noise, output noise, step down converters, buck converters, MAX1653EVKit
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设计指南 986

摘要 : Input and output noise in buck (step-down) converters can concern the system designer. This application note provides a theoretical explanation of the individual contributions of conducted noise on the input and output sides of buck converters. These equations will allow the power-supply designer to optimize components for noise immunity.

- The equations assume continuous conduction above 0A. This assumption describes the current flow in the inductor. Depending on the components used and on the load and the topology of the buck converter, the current flow through the inductor can look like that shown in Figure 1. The middle graph of
- The load is a constant DC load. This assumption needs to be made for practical reasons. While assumption 1 is a reasonable assumption for most applications, this second assumption is most likely not true. In a typical buck-converter application, the current draw of the load will fluctuate. This fluctuation will cause noise, due to the finite response time of the converter and the equivalent series resistance (ESR) of the output capacitor (explained later), among other things. To calculate the output noise due to this fluctuation, the characteristics of the load need to be known. That is, of course, impossible for this application note.
- The converter is 100% efficient. This again is a practical consideration. The equations would be unwieldy if this assumption was not made. Most modern buck converters have excellent efficiency and the amount of error introduced by this assumption is minimal.

The bottom graph of Figure 1 (Graph C) shows an example of continuous conduction where the current through the inductor drops below 0A. For the current to drop below 0A, the converter must have synchronous rectification and be designed to allow for that type of operation. With such a converter the current will typically, but not always, go below 0A under light-load conditions.

Whether the converter is synchronously rectified or not, continuous conduction above 0A will tend to happen at higher loads, as shown in the top graph in Figure 1. Thus, the equations listed in this application note should be appropriate when the converter is operating close to maximum loading.

Use Equation 1 below to test a particular design. If this inequality is met, the converter is operating in continuous conduction above 0A and the first assumption is satisfied.

V

V

f = the frequency at which the buck regulator is switching

L = the value of the inductor

I

A more complete model for a MOSFET is shown in

This model adds inductances and capacitances to the first-order model in Figure 2. The three capacitors shown are:

- C
_{GD}= Capacitance from the gate to the drain - C
_{GS}= Capacitance from the gate to the source - C
_{DS}= Capacitance from the drain to the source

- C
_{GD}= 120pF - C
_{GS}= 470pF - C
_{DS}= 180pF

All capacitors have what looks like a resistor in series with its capacitance. This resistor is referred to as the equivalent series resistance (ESR) of the capacitor. ESR varies significantly with the type of capacitor used. Ceramic capacitors typically have very low ESR; the average aluminum electrolytic capacitor can have high values of ESR; and tantalums capacitor EST values fall somewhere in between. In recent years, there have been a number of specialty capacitors designed to minimize ESR. Below is a listing of some examples:

- AVX TPS series. Example: 10V, 100µF capacitor with an ESR as low as 0.065Ω at 100kHz
- Kemet® A700 series. Example: 6.3V, 100µF capacitor with an ESR as low as 0.03Ω (max) at 100kHz
- Panasonic® ECJ series. Example: 16V, 4.7µF capacitor with an ESR as low as 0.017Ω (max) at 100kHz

Also in this model is the equivalent series inductance (ESL) of the capacitor. Some typical inductances for ceramic chip capacitors are listed below:

- 0.1µF at 1.7nH
- 0.01µF at .84nH
- 1000pF at 1.7nH

The catch diode used on some buck converters can be modeled as an inductance in series with a capacitor when reversed biased. The MBR030 used on the MAX1653 evaluation board has a capacitance of approximately 55pF when reversed biased with 8V. This capacitance varies significantly with bias voltage. The inductance is not listed in the data sheet, but is probably on the order of 1nH to 2nH.

This AC current working against the output capacitor's finite capacitance and ESR generates the output noise.

The first noise source we will discuss is finite output capacitance. Assuming for the moment that the output capacitor is ideal and that there is no ESR, the voltage on the capacitor is given by the age-old capacitor equation, V = I/C∫idt. With a little math, this formula can be represented as Equation 2. Equation 2 calculates the peak-to-peak output noise due to a finite output capacitance. It is interesting to note that the output noise is independent of the load current.

V

V

f = the frequency at which the buck regulator is switching

C

L = the value of the inductor

R

V

Minimizing this source of noise is academically simple: just increase the value of the output capacitance. If there were no ESR, this would truly be the case. However, choosing a larger capacitor can, under some circumstances, actually increase the output noise if the ESR of the capacitor is larger.

V

V

f = the frequency at which the buck regulator is switching

L = the value of the inductor

R

V

Choosing the correct output capacitor is critical for a low-noise design. The correct capacitor balances cost, low ESR, and high capacitance.

V

V

f = the frequency at which the buck regulator is switching

L = the value of the inductor

I

V

C

V

V

f = the frequency at which the buck regulator is switching

L = the value of the inductor

I

R

V

While the noise contributions from the input capacitance and ESR are fairly intuitive, this noise source is much less obvious. We can redraw the typical synchronous buck converter shown in Figure 6 to include all the nonideal components, e.g., the MOSFETS, catch diode, input capacitor and traces (

Figure 12 can be simplified into

The equations that govern this RLC circuit with respect to our simplified model are given below:

When the buck converter uses an n-channel MOSFET on the high side, the variables given in the above equations can be defined as:

V

L

L

V

τ = the ring-down time constant

R

R

C

The case where a p-channel MOSFET is used on the high side is not as simple. When an n-channel MOSFET is used, the capacitance of the high-side switch can be ignored. This is because a floating gate driver is used, and it basically shorts out most of the high-side MOSFET's capacitances. In the case of a p-channel MOSFET, a floating gate driver is not used, and the capacitances cannot be ignored. Therefore, our aggressive oversimplification of the circuit is not as nearly as accurate in the case of a p-channel supply as it is for an n-channel supply. However, the basic concepts and the solutions are the same.

To check the relative accuracy of our simplified circuit in Figure 14, we compare the response of the MAX1653EVKIT (Figure 11) with the ideal waveform (Figure 15). The ideal waveform was generated using values obtained from the typical components used on the MAX1653 EV board. The MAX1653EVKIT is ideal for comparison purposes, because it uses a high-side n-MOSFET.

The first thing to notice is that the first low-going cycle on the EV kit is not as big as that predicted by our simple model. This is primarily because of the finite turn-on time of the MOSFET: the MOSFET does not instantaneously go from high impedance to low impedance. This transition takes time. In the case of the MAX1653EVKIT, this transition is on the order of 5ns to 15ns. Because this transition time is roughly on the same order as the period of our ringing, the first cycle gets attenuated. This works in our favor to reduce the peak-to-peak noise. Consequently, except for the first low-going cycle, our simplified model matches the lab results as well as can be expected.

Now that we understand the source of this ringing, how do we minimize it? Looking at Equation 6, we find that the noise is based on three variables: the input voltage (over which we have little control), the input capacitor's series inductance, and the sum of the inductances in the circuit. It becomes obvious (both mathematically and intuitively) to use input capacitors that have small series inductances. In addition, placing a small, low-inductance ceramic chip capacitor in parallel with the bulk capacitance can reduce the size of this noise. Keep these capacitors as close as possible to the MOSFETs (and/or catch diode). See

At this point it is appropriate to mention measuring techniques. Good measurement techniques are a good idea in general, and are critical in trying to measure input-capacitance ESL noise. When using a scope probe, keep the ground lead as short as possible. Connect both the signal portion of the probe and the ground lead directly across what you are trying to measure. Remember that this noise source is due to inductances on the order of nHs. It does not take much trace length to introduce nHs of inductance and ruin your measurement.

If further reduction of this noise source is necessary, some input-supply filtering can virtually eliminate the noise. The simplest and most economical way is to separate the V

Noise due to Finite Capacitance | |

Input Noise | |

Output Noise | |

Noise due to ESR of Capacitor | |

Input Noise | |

Output Noise |

V

V

f = the frequency at which the buck regulator is switching

C

C

L = the value of the inductor

I

R

R

V

V

V

V

Note: The noise from the different sources is not in phase and, therefore, cannot be directly added.