HFAN-08.2.0: How to Control and Compensate a Thermoelectric Cooler (TEC)
This application note briefly discusses the origin and history of TEC design and then presents an overview of basic TEC operation. Issues with TEC control and compensation follow. The article concludes with a detailed analysis and equations for optimizing a TEC.
IntroductionIn 1821 Thomas Seebeck discovered that when two conductors of different materials were joined together in a loop and a temperature differential was present between the two junctions, a current flowed through the loop. Twelve years later, J. C. Peltier demonstrated the opposite effect: by cutting one of the conductors in the loop and forcing a current through the loop, a temperature differential was observed between the two junctions. Because of the materials available at the time, the resistive heat generated by the large currents involved dominated the Peltier effect. With recent material advances, these junctions have become more practical for use as thermoelectric heat pumps, performing the same function as fluorocarbon-based vapor compression refrigeration. While still not as efficient as vapor-cycle devices, these junctions have no moving parts or working fluid and can be very small in size.
Basic Theory of OperationBecause the Peltier effect can be controlled linearly with electricity, the thermoelectric cooler (TEC) has been found in many applications involving precision temperature control. The temperature-critical components, a TEC, and a temperature monitor are integrated into a single thermally engineered module. TEC control requires a reversible power source capable of providing positive and negative voltages. To accomplish this from a single supply, an H-bridge circuit can be used. While linear supplies offer low noise, their poor efficiency requires large components and added thermal insulation to prevent the regulator waste heat from loading the cooler. Alternatively, two synchronous buck circuits with complementary drivers provide a higher efficiency supply that can deliver bipolar power from a single positive supply. Forced pulse-width-modulation (PWM) control of the two output voltages allows current to be sourced and sinked. During current sinking, power is recovered and sent back to the supply line.
The small size of the TEC has allowed precision thermal control of individual components such as fiber optic laser drivers, precision voltage references, or any other temperature-critical device. TECs can also heat by reversing the current.
TEC Power ControlThe MAX1968 and MAX1978 are highly integrated H-bridge PWM switch-mode drivers designed for Peltier TEC modules.
The MAX1968 is a cost-effective solution for controlling TECs because it integrates the four power switches and the PWM control on a 28-pin thermally enhanced TSSOP-EP package. Packaged in a 48-pin TQFN-EP, the MAX1978 includes all the circuitry of the MAX1968 as well as the amplifiers necessary to build the thermal feedback loop. The MAX8520 and MAX8521 offer the smallest PCB footprint by using a 20-pin TQFN (MAX8520) or 36-bump WLP (MAX8521) package. An exposed paddle on the underside of the MAX1978 allows its package to dissipate as much as 3.2W and provide bipolar ±3V at 3A from a single 5V source. Switching is selectable at 500kHz or 1MHz. Independent positive and negative output current limits and a voltage limit are integrated on the chip and can be set using external resistors. An analog control signal precisely sets the TEC current regardless of the TEC voltage. The highly integrated MAX1978 provides a cost- and size-effective solution for driving and controlling a TEC and only requires passive external components for the control loop.
Using a Control Loop to Regulate TEC TemperatureFor precision temperature control, a local monitor inside or near the TEC module sends temperature information that is compared with a reference, generating an error signal. This error signal is amplified and sent to the TEC. The TEC then changes the local monitor temperature, thus completing the loop. Like any control loop, steady-state accuracy is related to the DC loop gain. Given the large thermal mass, it can take tens of seconds for the temperature monitor to respond to TEC changes. Consequently, compensation of the TEC and monitor loop can require a slow integrator to avoid oscillations and overshoot. Because, finally, the integrator requires large time constants, it can be difficult to find high-value capacitors with low enough leakage to achieve high DC gain. Therefore, to achieve stability the smallest size integrator capacitor must be selected.
To begin to compensate a thermal loop, the thermal response of the TEC module must be understood. The low-frequency response of the TEC module can be measured by using the MAX1968 or MAX1978 as a driver for the TEC, the internal thermistor in the module, and a network analyzer with subhertz capacity like the Agilent® HP3562A Dynamic Signal Analyzer. Most laser-diode TEC modules behave approximately like a two-pole system. The first pole starts at 20mHz and a second pole at 1Hz. If a network analyzer is not available, measure the DC gain and assume 20mHz and 1Hz poles to approximate the TEC response. Although this model is crude, it helps us to understand the limitations in closing the loop. Since the modules have a slow 20mHz pole, a 90-degree phase shift is expected from the TEC module up to 1Hz. Thereafter, the second pole creates a potentially oscillatory condition.
The TEC response in cooling mode is shown graphically with solid lines in Figure 1. Because TECs have four times stronger heating capacity than cooling for the same input current, this response can vary by 6dB. Other factors such as heat sinking, ambient temperature, and heat generated internally in the module can also change the response. Modules from different manufactures can have varying responses as well. If a TEC module with no internal thermistor is used, characterize the frequency response of the selected TEC and thermistor separately.
Figure 1. TEC frequency response.
Compensating the LoopThe proportional integral derivative (PID) controller shown in Figure 2 is a good starting point. From here, adjustments can be made to optimize the TEC response. For the highest DC gain, an integrator is needed. The integrator in Figure 2 is formed by C2 and adds a third pole which, without R3 (Figure 2), makes stability impossible. R3 inserts a zero into the integrator before unity-gain crossover; ideally this should occur at the first pole, 20mHz. It can be pushed up to 70mHz without any stability issues. Although this process creates a second-order response from 20mHz to 70mHz, the phase never reaches oscillatory conditions (180 degrees). This is shown with red dotted lines in Figure 1.
Figure 2. PID controller circuit.
The differential network, formed by C1, R1, and R2 in Figure 2, adds another zero to cancel the second 1Hz pole in the TEC module. This zero provides extra phase margin to close the loop at a higher frequency. This is illustrated in Figure 1 by the blue dashed lines. While the fast response associated with high loop bandwidth is not needed, the high DC gain and small capacitors are. The compensator uses C3 to rolloff the gain at 30Hz and thus reduces noise injection into the loop. In TEC applications this circuit allows the loop to crossover at 2Hz and provides good phase margin over a wide range.
The TEC thermal Loop in Figure 3 is a compensation example for a 2Hz crossover. Selecting R3 as high as possible allows the smallest integrator capacitor, C2. This approach, however, comes at the cost of higher gain in the PID stage. Because we must insert a zero at 70mHz, we use the relation:
fZ1 = 1/(2π × C2 × R3)With fZ1 = 70mHz and selecting R3 = 243kΩ, it follows that C2 = 9.36µF. We select 10µF for the design. Now we select R1 = 10kΩ. This allows sufficient gain in the front-end amplifier (U2) to reduce the reflected integrator (U1) errors while maintaining reasonable capacitor sizes.
Figure 3. Thermal loop block diagram.
Now we must insert a zero to cancel the second pole of the TEC at 1Hz. Because we desire good phase margin, we insert the zero at the desired crossover frequency divided by at least 5, or 0.4Hz. This gives a better phase margin at the crossover frequency. We then terminate the zero by placing the pole created by R1 at least 5 times higher than the crossover frequency, or 10Hz. This limits the gain of the integrator section after the loop has crossed over.
fZ2 = 1/(2π × C1 × R2)And with fZ2 = 0.4Hz and R2 = 510kΩ, it follows that C1 = 0.78µF. We select 1µF for the design. To find R1 we use the relation:
f3 = 1/(2π × C1 × R1)And with f3 = 10Hz and C1 = 1µF, we find that R1 = 15.9kΩ. We use 10kΩ to provide better phase margin. We then must set the rolloff frequency at 30Hz. With R3 = 243kΩ, fC = 30Hz, and:
fC = 1/(2π × C3 × R3)We find that C3 = 0.022µF.
Now that the TEC response has been optimized, the system gain must be adjusted for a crossover at 2Hz. Graphically we can see from Figure 1 that at 2Hz the uncompensated transfer function (the solid line in Figure 1) has -30dB gain. If we desire a 2Hz unity gain crossover, we must provide +30dB gain at 2Hz. Because U1 and its components have gain at 2Hz, we must subtract this gain from the total needed system gain to find the front-end gain. R3 and C1 define the gain for U1. At 2Hz, R1, R2, C2, and C3 can be neglected. The reactive impedance of C1 at 2Hz can be found using:
XC = -j/(2π × fC × C1With C1 = 1µF and fC = 2Hz, it follows that:
XC = -j79.6kΩThe magnitude of the gain G for U1 is:
G = |R3/XC|With R3 = 243kΩ and XC = -j79.6kΩ, G = 3.05 or 9.7dB. A full analysis of this gain that does not neglect R1, R2, C2, and C3 yields G = 3.11 or 9.8dB, thus validating our assumption. We now must provide 20.3dB in the front-end for a unity gain crossing at 2Hz.
The front-end gain section serves two functions: it reduces errors from the integrator in U1, and samples the temperature information from the thermistor. The DC gain set by R4, R5, and U2 (Figure 3) needs to be high enough to ensure that the error signal is not overridden by the PID compensation section. With R4 = 10kΩ and R5 = 100kΩ, the front-end gain is 11 or 20.8dB, more than enough to overpower the 9.7dB of the PID compensation section. The temperature reading from the thermistor is passed to the PID control section as an error signal. The error signal represents the difference between the actual temperature (THERM) and the desired temperature (SET POINT IN). The error signal at the output of U2 can be calculated as:
Where 1.5V is the value of the reference connected through the 10kΩ resistor to THERM; RT is the resistance of the thermistor; and VSET is the voltage at SET POINT IN.
Regulating TEC Temperature with the Compensated Thermal LoopAn example of the entire loop and the compensation values is shown in Figure 3. By knowing what resistance value RT will be at a given temperature, VSET can be chosen to automatically regulate the temperature of the thermistor to that value. This example uses a jumper-selectable digital-to-analog converter (DAC) or a potentiometer to control VSET. The temperature is regulated by sending the error signal to the PID compensation section, which controls the analog input to the TEC driver until the error signal approaches 0. Because of the good phase margin provided by the PID compensator, this circuit is very tolerant of TEC gain variations in heating or cooling modes.
Selecting ComponentsSelecting components for this circuit will depend on the specific requirement needed for an application. The MAX1978 provides on-chip amplifiers which are sufficient for this design topology. If the MAX1968, MAX8520, or MAX8521 are used, then an op amp with low offset-voltage drift like the MAX4477ASA is a good choice for U2 and U3. Because of the low signal level at the thermistor, shielded wire should be used. U1 should have ultra-low leakage current to avoid DC offsets generated by the high circuit impedance. The MAX4475ASA op amp with 150pA (max) leakage current is a good choice. The components around U1, in particular C2 and C3, should be selected with the highest leakage resistance; C2 needs the lowest thermal drift possible. Polystyrene film capacitors are the best choice, but they are very large and expensive. Ceramic capacitors are a good choice, but the larger values can leak enough to cause gain errors. Do not use electrolytic or tantalum capacitors. A guard ring constructed with a PC-board trace placed around and under the inverting pin on U1 and its components should be connected to the noninverting pin of U1. The guard ring intercepts any stray currents that can induce errors in the summing junction. Solder flux, moisture, and fiberglass PC boards can contribute to leakage currents and a guard ring can improve these effects. Conformal coating the board and its components can help keep contaminants from interfering with circuit performance.
Testing the TEC Control Loop and ModuleTesting the loop can be done with a unit-step function. A simple change in temperature set point should induce a response in the thermistor that converges on the new temperature set point with very little overshoot. Ringing observed in the step response indicates poor phase margin at the crossover frequency. By noting the ringing frequency and the number of rings, adjustments can be made in the DC gain (crossover frequency) or the compensation circuit (phase margin) until an acceptable response is met.
By using this method and with some insight into TEC behavior, a TEC loop can be compensated without a network analyzer. Even with the help of a network analyzer, the system should be checked in heating and cooling modes with a unit-step response. Heating the TEC in cooling mode and cooling in heating mode presents the worst cases. DC errors in the loop can be measured with a 6-digit meter with a 1GΩ input impedance such as the Agilent 34401A set up to measure the difference between SET POINT IN and THERM (Figure 3). This error should be in the 100µV range. Noise can be measured at the same points with a differential amplifier like the Tektronix® ADA400A and a scope. With 100Hz bandwidth, this error should be under 20µVP-P.