Successive-approximation-register (SAR) analog-to-digital converters (ADCs) are frequently the architecture of choice for medium-to-high-resolution applications, typically with sample rates fewer than 5 megasamples per second (Msps). SAR ADCs most commonly range in resolution from 8 bits to 20 bits and provide low power consumption as well as a small form factor. This combination makes them ideal for a wide variety of applications, such as automatic test equipment, battery-powered equipment, data acquisition systems, medical instrumentation, motor and process control, industrial automation, telecommunications, test and measurement, portable systems, high-speed closed-loop systems, and narrowband receivers.
The MAX11905 is Maxim Integrated's highest resolution SAR ADC, which runs 1.6Msps at 20 bits, and offers dynamic performance of 98.3db SNR and -123dB THD. There are two different evaluation kits available for the MAX11905. Choose between the EV kits according to two different analog front-ends, the MAX11905EVKIT# (Figure 1), which uses the MAX9632 op amps or the MAX11905DIFEVKIT# (Figure 2), which uses the MAX44205 differential op amp. Both EV kits use the Avnet ZedBoard™ for communication to a PC.
Figure 1. MAX11905EVKIT photo.
Figure 2. MAX11905DIFEVKIT photo.
Another one Maxim Integrated's popular ADC is the MAX11156, which is an 18-bit ADC running at 500ksps. It provides dynamic performance of SNR 94.6dB and THD -105dB at 10kHz. The MAX1115X/6X EV kit (Figure 3) can evaluate this device and the entire family of MAX1115X/6X products.
Figure 3. MAX1115X/6XEVKIT photo.
Each device in the following table is part of a family of high-end ADCs. Maxim Integrated also offers a family of ADCs with lower resolution and sampling rate.
|Part No.||Channel(s)||Resolution (Bits)||Sampling Rate (sps)|
Sigma-delta analog-to-digital converters (ADCs) are used predominately in lower speed applications requiring a trade-off of speed for resolution by oversampling, followed by filtering to reduce noise. 24 bit sigma-Delta converters are used in applications such as automation test equipment, high-precision portable sensors, medical and scientific instruments, and seismic data acquisitions.
Maxim Integrated offers the MAX11270 which is a 24-bit delta-sigma ADC that achieves an excellent +130db SNR while dissipating an ultra-low 10mW of power. The following is a link to the MAXREFDES75# reference design (Figure 4) that shows how the MAX11270 is used in a weigh scale system.
Figure 4. MAXREFDES75# featuring the MAX11270 sigma-delta ADC.
The MAX11216 is an ultra-low-power and wide dynamic range 24-bit sigma-delta ADC designed for seismic applications.
Figure 5 is a block diagram for this application.
Figure 5. MAX11216 block diagram.
Integrating ADCs provide high resolution and can provide good line frequency and noise rejection. Having started with the ubiquitous ICL7106, these converters have been around for quite some time. The integrating architecture provides a novel yet straightforward approach to converting a low bandwidth analog signal into its digital representation. These type of converters often include built-in drivers for LCD or LED displays and are found in many portable instrument applications, including digital panel meters and digital multi-meters.
Flash analog-to-digital converters, also known as parallel ADCs, are the fastest way to convert an analog signal to a digital signal. They are suitable for applications requiring very large bandwidths. However, flash converters consume a lot of power, have relatively low resolution, and can be quite expensive. This limits them to high frequency applications that typically cannot be addressed any other way. Examples include data acquisition, satellite communication, radar processing, sampling oscilloscopes, and high-density disk drives.
The pipelined analog-to-digital converter (ADC) has become the most popular ADC architecture for sampling rates from a few megasamples per second (MS/s) up to 100MS/s+, with resolutions from 8 to 16 bits. They offer the resolution and sampling rate to cover a wide range of applications, including CCD imaging, ultrasonic medical imaging, digital receiver, base station, digital video (for example, HDTV), xDSL, cable modem, and fast Ethernet.
Two Step analog-to-digital converters (ADCs) are also known as subranging converters and sometimes referred to as multi-step or half flash (slower than Flash architecture). This is a cross between a Flash ADC and pipeline ADC and can achieve higher resolution or smaller die size and power for a given resolution are needed vs. a Flash ADC. Example MAX153.
|FLASH (Parallel)||SAR||DUAL SLOPE (Integrating ADC)||PIPELINE||SIGMA DELTA|
|Pick This Architecture if you want:||Ultra-High Speed when power consumption not primary concern?||Medium to high resolution (8 to 20 bits), 5Msps and under, low power, small size.||Monitoring DC signals, high resolution, low power consumption, good noise performance ICL7106.||High speeds, few Msps to 100+ Msps, 8 bits to 16 bits, lower power consumption than flash.||High resolution, low to medium speed, no precision external components, simultaneous 50Hz/60Hz rejection, digital filter reduces anti-aliasing requirements.|
|Conversion Method||N bits - 2N - 1 Comparators Caps increase by a factor of 2 for each bit.||Binary search algorithm, internal circuitry runs higher speed.||Unknown input voltage is integrated and value compared against known reference value.||Small parallel structure, each stage works on one to a few bits.||Oversampling ADC, 5Hz to 60Hz rejection programmable data output.|
|Encoding Method||Thermometer Code Encoding||Successive Approximation||Analog Integration||Digital Correction Logic||Over-Sampling Modulator, Digital Decimation Filter|
|Disadvantages||Sparkle codes/metastability, high power consumption, large size, expensive.||Speed limited to ~5Msps. May require anti-aliasing filter.||Slow Conversion rate. High precision external components required to achieve accuracy.||Parallelism increases throughput at the expense of power and latency.||Higher order (4th order or higher) - multibit ADC and multibit feedback DAC.|
|Conversion Time||Conversion Time does not change with increased resolution.||Increases linearly with increased resolution.||Conversion time doubles with every bit increase in resolution.||Increases linearly with increased resolution.||Tradeoff between data output rate and noise free resolution.|
|Resolution||Component matching typically limits resolution to 8 bits.||Component matching requirements double with every bit increase in resolution.||Component matching does not increase with increase in resolution.||Component matching requirements double with every bit increase in resolution.||Component matching requirements double with every bit increase in resolution.|
|Size||2N - 1 comparators, Die size and power increases exponentially with resolution.||Die increases linearly with increase in resolution.||Core die size will not materially change with increase in resolution.||Die increases linearly with increase in resolution.||Core die size will not materially change with increase in resolution.|