解决方案指南 7599

New Octal Pin Electronic Driver for Next Generation ATE Systems

By: Bob Gee

摘要 :

Automatic Test Equipment (ATE) technology follows the trends of semiconductor ICs, the devices they test. With increased bandwidth, integration, and cost pressure, next generation ATE systems need higher density and higher throughput to keep up with the latest semiconductor demands.


Introduction

The technology boom driving the world’s demand for semiconductors is still going strong, driven by multiple megatrends. Wireless infrastructure, Internet of Things, artificial intelligence, data centers, and electric vehicles are examples of applications driving the increased demand for advanced semiconductors ICs. With more features packed into each individual IC, test requirements increase and become more challenging to keep costs down. How can semiconductor manufacturers increase complexity of their end products, but decrease their test costs?

Test Systems are Not Standardized

Broadly, the semiconductor development process includes design, fabrication, and test. Today, IC designers use EDA (electronic design automation) software tools. These tools are standardized and greatly streamline the design process. The fabrication equipment of wafers is also standardized to some extent, as many processes and equipment perform from generation to generation. The same cannot be said of ATE systems. A lack of standards and the increased complexity of ICs causes test costs to escalate. Studies have shown that packaging and test account between 50% to 70% of the total product cost.

Test Cost Reduction

An obvious way to reduce test cost is to adopt higher parallelism and test multiple parts simultaneously. Whenever an ATE system tests more parts in parallel, throughput improves. For example, if the previous testing platform could test four devices in parallel with a total test time of 10 seconds, each device test is 2.5 seconds. Using a hypothetical cost of $0.02 per second, then each device has a $0.05 test cost. By upgrading the ATE system to an octal site or even a 16-site tester, there is a dramatic drop in test costs, $0.025 and $0.0125, respectively. This test cost savings of 75% shaves off $0.0375 from the original test cost, in comparison with the 16-site test setup.

Next, imagine if total test time could be reduced by half. Since ATE production floor test engineers will have maximized the resources to test devices, the way to reduce test time is to increase the speed of the driver signals, to the device under test (DUT), and comparator signals, back to the FPGA. A 2X upgrade in the pin electronics speed, where the driver and comparator ICs reside, cuts test time in half. The math to calculate test cost is just as straightforward in the previous example. Instead of 10 seconds, the testing of 16 devices takes 5 seconds. This translates to a test cost of $0.00625 per device, half of $0.0125. While real-world test time varies, this hypothetical example clearly demonstrates the potential savings from a faster system and higher density card.

Higher Density and Speed

The pin electronics driver board mentioned previously has the driver and comparator ICs. The ATE block diagram in Figure 1 shows where the MAX32007 resides (DCL + DAC + SWITCHES box). The MAX32007 is ADI’s latest release, an eight-channel 3Gbps pin driver.

General ATE System Block Diagram Figure 1. General ATE system block diagram.

The high-density, eight-channel, high-speed 3Gbps MAX32007 features an integrated 14-bit level-setting DAC, cable droop compensation, and slew-rate control for optimizing the waveform to the DUT.

Cable Droop Compensation

The waveform driven to the DUT and the return signal back can be attenuated or degraded due to long traces on the PCB and/or due to long or lossy coax cables. When waveforms are affected this way, the effective data rate degrades, or worse, the data is unusable, impacting the throughput and cost of the test. The MAX32007 incorporates a double time constant both long (CDRPL) and short (CDRPS) to the output waveform, which restores the rounded edges by a controlled amount of overshoot and undershoot.

General ATE System Block Diagram Figure 2. Conceptual representation for driver cable droop compensation.

The amount of compensation can be programmed by a 3-bit internal register from 0 to 10%. The scope shot in Figure 3 depicts an example of how cable droop compensation can help signal fidelity to overcome degraded waveforms over a 24-inch 50Ω coax cable. The outer green trace represents 10% compensation applied to the waveform and the inner trace shows 0% compensation.

Scope Shot of Cable Droop Compensation. Figure 3. Scope shot of cable droop compensation.

Conclusion

As semiconductor ICs continue to keep up with the latest demand in technology, so too must the automated test equipment required to test them. Pin electronic drivers play a key role in handling this surge in technology with higher density and higher data rate enables high throughput and lower test costs for next-generation devices.