were developed to meet the power sequencing requirements of the core processor and the I/O logic circuits in various xDSL and cable modem systems. Improper power sequencing can cause system latch-up or damage integrated circuits. Sequencing problems jeopardize quality and reliability and often cause intermittent failures that are difficult to detect. This application note describes ways to meet the IC manufacturers' recommended power sequencing specifications.
The MAX1964 provides a staggered output sequence. VOUT1
comes up first. When VOUT1
reaches ~90% of nominal value, VOUT2
is turned on. Similarly, when VOUT2
reaches ~90% of nominal value, VOUT3
is turned on. Figures 1
below show the schematic and the associated timing diagram of a typical circuit.
Figure 1. MAX1964 schematic.
Figure 2. Output staggering sequence (from top trace down: VOUT1, VOUT2, VOUT3, and POK).
Alternately, the MAX1965
provides output tracking sequencing, where all outputs are turned on at the same time, but track each other on the way up. This is useful when the core and I/O supplies must remain within a maximum delta when powering up. Figures 3
show the schematic and the associated timing diagram of a typical operating circuit using the MAX1965.
Figure 3. MAX1965 schematic.
Figure 4. Output tracking sequence (from top trace down: VOUT4, VOUT1, VOUT2, VOUT3, VOUT5, and POK).
As seen from Figure 4, after an initial offset of approximately one diode drop from VOUT1
, all outputs rise together. The circuit in Figure 3 focuses on having VOUT1
, and VOUT3
track very closely during power up, which are normally used for core and logic I/O supplies that need tracking. VOUT4
are typically used for line drivers supplies where tracking is not critical.