# Boost Power Stage Design Equations

摘要 : This application note explains how the integrated boost converter power stage is being constructed by selecting the appropriate external components to achieve a step up voltage powering other modules.

## Introduction

Switching regulators are always the choice when the system has high power requirements. They provide the high efficiency and compact PCB solution size for a satisfactory power supply. This application note provides equations to guide the selection of external components needed for a step-up switching regulator when achieving a boost voltage.

## Boost Converter Configuration

As a basic step-up switching regulator configuration shown in **Figure 1**, when the low-side switch is turned on at the beginning of a clock switching cycle, the high-side switch is turned off at the same time. V_{LX} equals ground voltage; when the low-side switch is turned off, the high-side switch is turned on within the rest time interval of a clock switching cycle, and V_{LX} equals output voltage V_{OUT}, neglecting the voltage drop across the high-side and low-side PowerFETs introduced by switching currents I_{HS} and I_{LS} flowing through the loop, respectively. The square wave signal appearing on the V_{LX} is passed through the LC filter, generating a constant output voltage V_{OUT}, which is controlled by the duty cycle D of V_{LX}.

Meanwhile, during the low-side switch ON time interval, the inductor current I_{LX} ramps up to store the energy of the inductor, and opposite to the high-side switch ON time interval, I_{LX} ramps down to deliver the energy stored inside the inductor to maintain the output load.

*Figure 1. Boost converter configuration*

*Figure 2. Boost converter waveform *

## Selecting the Inductor

When in continuous conduction mode, the power switch consumes power loss with each state in a switching cycle. The increased inductor current still equals the decreased inductor current. The duty cycle is arranged with the following equation:

Equation (1)

where the parameters are:

V_{OUT}: Regulated output voltage

V_{IN}: Supply input voltage

V_{DS1}: Voltage drop across HS switch

V_{DS2}: Voltage drop across LS switch

The duty cycle is determined simply by the input voltage and output voltage when neglecting the V_{DS1} and V_{DS2}:

Equation (2)

The higher inductance value generates a smaller current ripple ΔI_{LX} and peak current value I_{PEAK}, which determines the maximum load current the switching regulator IC outputs, also inducing a smaller input voltage ripple. The I_{PEAK} should be less than the minimum value of the ILIM the IC can provide.

The switching regulator IC data sheet provides the inductor selection range, normally a fixed nominal value \pm tolerance%, and the device internal slope compensation is optimized for the external inductor value selected within the acceptable range. Once the inductor value is selected, the peak current is derived as DC input load plus half inductor ripple current.

The inductor ripple current and peak current are expressed as:

Equation (3)

Equation (4)

where the parameters are:

V_{IN}: Supply input voltage

D: Duty cycle derived from **Equation (2)**

f_{sw}: Switching frequency on system

L: Inductor value

I_{LOAD}: Load current required from IC

The root mean square (RMS) current flowing through the inductor is:

Equation (5)

where the parameters are:

I_{LOAD}: Load current required from IC

ΔI_{LX}: Inductor ripple current calculated value from **Equation (3)**

Select inductors having a higher RMS current rating to avoid overheating impacting the efficiency and performance. The saturation current of the inductor stated from the data sheet should be larger than the maximum value of I_{PEAK} in a given range of V_{IN} so that the inductance value does not drop too much by a certain number. Smaller inductor value has low cost and saves PCB area, but has larger current ripple, conducting more AC core power loss dissipated on it, combining with the conduction power loss from the DCR value of the inductor. The significant power dissipated on inductor also heat ups the whole compact solution area, lowering efficiency, especially for heavy input average current.

## Selecting the Input Capacitor

The input voltage ripple is contributed by the capacitor elements capacitance and equivalent series resistance (ESR) in steady state. Use low ESR, X7R ceramic capacitors to minimize the input voltage ripple.

The input capacitance with a specific input voltage ripple is expressed as:

Equation (6)

where the parameters are:

ΔI_{LX}: Inductor ripple current calculated value from **Equation (3)**

f_{sw}: Switching frequency on system

ΔV_{IN}: Input voltage ripple requirement

The input voltage ripple contribution from ESR is expressed as:

Equation (7)

where the parameters are:

ΔI_{LX}: Inductor ripple current calculated value from Equation (3)

R_{ESR}: Equivalent series resistance of input capacitors

The actual ceramic capacitance should be larger than the value calculated above to give some margin on the capacitance loss by DC bias voltage derating. Follow the data sheet component selection guide for minimum ceramic capacitance needed to stabilize the input voltage. One 0.1µF ceramic capacitor should be preferably placed in parallel, decoupling high frequency noise on input. Add aluminum bulk capacitance to provide large current during load transient and keep an allowable input voltage deviation.

## Selecting the Output Capacitor

When the high-side switch is in the ON state, the switching current flowing on the IC output path carries switching noise, and the output capacitor filters out most noise effectively and reduces output voltage ripple. The larger the load current, the larger the voltage ripple that is seen on the output. Place the output capacitor as close to the switching regulator as possible.

Calculate the output capacitance for a specified output voltage ripple as:

Equation (8)

where the parameters are:

I_{LOAD}: Load current required from IC

D: Duty cycle derived from **Equation (2)**

f_{sw}: Switching frequency on system

ΔV_{OUT}: Output voltage ripple requirement

The output voltage ripple contribution from ESR is expressed as:

Equation (9)

where the parameters are:

I_{LOAD}: Load current required from IC

D: Duty cycle derived from **Equation (2)**

ΔI_{LX}: Inductor ripple current calculated value from **Equation (3)**

R_{ESR}: Equivalent series resistance of output capacitors network

Use low ESR ceramic capacitors to minimize the output voltage ripple when large ripple current is flowing through output capacitors. X7R dielectric material has better temperature characteristics to handle less capacitance change with temperature rise on capacitors.

## Adjusting the Output Voltage

The output voltage is set either by the fixed internal resistor divider, or adjusted by the external resistor network, if applicable, with feedback to switching regulator IC. The current I_{RT} flowing through the top resistor R_{T} should be larger than 100 times of the leakage current I_{FB} going into the feedback pin of IC to maintain the voltage accuracy on the output. Add a small feedforward capacitor C_{FF} in parallel with top resistor R_{T} to produce a boost zero in the feedback loop to optimize phase margin.

Follow the data sheet to choose the recommended bottom resistor R_{B} in **Figure 3** as a smaller value in kΩ. Then, the top resistor R_{T} is calculated as:

Equation (10)

where the parameters are:

R_{B}: Bottom resistor in adjustable resistor divider network as suggested from the data sheet

V_{OUT}: Desired output voltage

V_{FB}: Regulated feedback voltage

*Figure 3. Adjustable resistor divider network configuration*

## Power Dissipation

At a particular operating condition, the output power P_{OUT} is fixed with the given output voltage V_{OUT} and load current I_{OUT}, and the less the power loss PLOSS of the system, the higher the efficiency η (η = P_{OUT}/(P_{OUT} + P_{LOSS})). The power loss of an inductor comprises DC conduction loss (I_{OUT}^{2} × R_{DCR}) and AC core loss, which is provided by the inductor manufacturer on the specific inductor power model neglected in **Equation (11)**.

The power dissipated on the switching regulator IC is expressed as:

Equation (11)

where the parameters are:

V_{OUT}: Regulated output voltage

D: Duty cycle derived from **Equation (2)**

I_{LOAD}: Load current required from IC

η: Efficiency of regulator

R_{DCR}: Inductor DC resistance

The power consumption inside the device is transformed into heat, increasing the junction temperature. The junction temperature of the die T_{J} exceeds the maximum limit of the operating temperature T_{JMAX} indicated in the data sheet, and degrades the lifetime and affects product reliability.

To estimate the junction temperature in a given ambient T_{A}:

Equation (12)

where the parameters are:

T_{A}: Ambient temperature

ϴ_{JA}: Thermal resistance of junction to ambient as suggested in the data sheet

P_{LOSS}: Power loss inside the device from **Equation (11)**