Introduction

The MAXREFDES74# is a high-speed, 18-bit precision data-acquisition system featuring the MAX11156 ADC and MAX5318 DAC. The reference design allows for both unipolar and bipolar modes of operation from a single +15V to +20V DC source. The unipolar mode operates as expected; however, the bipolar mode contains a potential power sequencing issue upon startup if J6 is in position 1-2. This only applies to boards using a 100kΩ resistor for R31.

The reference design uses a single +15V to +20V power source, an on-board transformer to create power isolation, and relies on several regulators to generate the power rails necessary for board operation. When operating in bipolar mode, J6 connects the MAX664 regulator output to AVSS of the MAX5318. Figure 1 provides a block diagram of the connections between the MAX5318 and MAX664 along with the power supplies to each chip.

Figure 1. MAXREFDES74# schematic for DAC AVSS generation.

On the MAXREFDES74#, the +5V supply to the MAX5318 always powers on prior to the -1.3V supply. Before the MAX664 can provide a regulated output, a ~0.65V appears on the AVSS pin of the MAX5318. Based on the schematic connections, this positive voltage appears on the V_OUT1, V_OUT2, V_SET, and SENSE pins on the MAX664, raising these pins above their absolute maximum value of +0.3V as specified in the MAX664 data sheet. Figure 2 shows an oscilloscope capture of the power-on sequencing when conditioned for bipolar operation. The positive rail powers on first and causes a positive voltage to appear on AVSS of the MAX5318.

Figure 2. MAX5318 bipolar power-up sequence. Ch1 = AVDD (TP11), Ch2 = AVSS (TP14), Ch3 = MAX664 V_OUT1V_OUT2 (J6).

Since the absolute maximum voltage on V_SET, SENSE, V_OUT1, and V_OUT2 are exceeded when the positive supply powers on first, internal components of the MAX664 are biased incorrectly and hold the MAX664 in an “off” state. Figure 3 displays the internal block diagram of the MAX664. When V_SET is above -50mV, the SENSE pin of the MAX664 can be used to set the regulator output voltage through an internal resistor divider compared to an internal -1.3V reference. When V_SET drops below -50mV, its voltage is directly compared to the internal -1.3V reference. Since both pins are improperly biased above GND, the negative output rail is never generated and the board does not operate properly.

Figure 3. Internal block diagram of the MAX664.

Solutions

There are several solutions that range in complexity to correct the power supply problem when operating MAXREFDES74# in bipolar mode:

1. When powering on the reference design, have J6 connect pins 2-3 or leave J6 unconnected. Disconnecting the MAX664 from the MAX5318 allows proper generation of the -1.3V rail. After power-on, switch J6 to connect 1-2, providing the negative supply to AVSS. The board is now ready to operate in bipolar operation.
2. Bypass the single +15V to +20V DC input and use dual power supplies. Connect +15V to TP9 with J17 in position 1-2. Connect -15V to TP23 with J24 in position 3-4. Connect the power supply grounds to any of the analog ground test points on the board (preferably TP22). With J6 in position 1-2, turn on the negative supply first and then the positive supply.
3. The best solution is to replace R31 with a 750Ω resistor. Replacing the resistor obtains the correct voltage rails ~14ms after applying supply power to the board. Figure 4 displays the scope capture of the startup sequence using a 770Ω resistor. R31’s small package can make it difficult to replace without damaging the board. Placing the 750Ω resistor in parallel with the original 100kΩ resistor yields the same result. There are several places on the board to insert the additional resistor. The easiest place to insert the resistor is between J6.2 and J6.3 on the bottom-side of the PCB.
   
   

   Figure 4. Startup sequence obtaining correct voltage rails. Ch3 = AVSS (TP14), Ch4 = AVDD (TP11)

4. Disconnect the MAX664 SENSE pin from the MAX5318 AVSS pin by cutting a trace. This solution treats the symptoms of the problem, but does not solve the root issue of the positive voltage generated on AVSS. After power-on, a positive voltage that exceeds the absolute maximum voltage still arises; however, having SENSE disconnected achieves correct voltages levels 700ms after power-on. Figure 5 displays the power-on sequencing when SENSE is disconnected.
   
   

   Figure 5. MAX5318 corrected power-up sequence. Ch1 = AVDD (TP11), Ch2 = AVSS (TP14), Ch3 = MAX664 V_OUT1/V_OUT2 (J6).